Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 72

indicates that the register contains a deferred exception token, and that its 64-bit data
portion contains an implementation-specific value that software cannot rely upon. In
floating-point registers, a deferred exception is indicated by a specific pseudo-zero
encoding called the NaTVal (see
on page 1:86
4.4.4.2 Control Speculation and Instructions
Instructions are divided into two categories: speculative (instructions which can be
used speculatively) and non-speculative (instructions which cannot). Non-speculative
instructions will raise exceptions if they occur and are therefore unsafe to schedule
before they are known to be executed. Speculative instructions defer exceptions (they
do not raise them) and are therefore safe to schedule before they are know to be
executed.
Loads to general and floating-point registers have both non-speculative (ld, ldf, ldfp)
and speculative (ld.s, ldf.s, ldfp.s) variants. Generally, all computation instructions
which write their results to general or floating-point registers are speculative. Any
instruction that modifies state other than a general or floating-point register is
non-speculative, since there would be no way to represent the deferred exception
(there are a few exceptions).
Deferred exception tokens propagate through the program in a dataflow manner. A
speculative instruction that reads a register containing a deferred exception token will
propagate a deferred exception token into its target. Thus a chain of instructions can be
executed speculatively, and only the result register need be checked for a deferred
exception token to determine whether any exceptions occurred.
At the point in the program when it is known that the result of a speculative calculation
is needed, a speculation check (chk.s) instruction is used. This instruction tests for a
deferred exception token. If none is found, then the speculative calculation was
successful, and execution continues normally. If a deferred exception token is found,
then the speculative calculation was unsuccessful and must be re-done. In this case,
the chk.s instruction branches to a new address (specified by an immediate offset in
the chk.s instruction). Software can use this mechanism to invoke code that contains a
copy of the speculative calculation (but with non-speculative loads). Since it is now
known that the calculation is required, any exceptions which now occur can be signalled
and handled normally.
Since computational instructions do not generally cause exceptions, the only
instructions which generate deferred exception tokens are speculative loads. (IEEE
floating-point exceptions are handled specially through a set of alternate status fields.
See "Floating-point Status Register" on page
propagate deferred exception tokens, but do not generate them.
4.4.4.3 Control Speculation and Compares
As stated earlier, most instructions that write a register file other than the general
registers or the floating-point registers are non-speculative. The compare (cmp, cmp4,
fcmp), test bit (tbit), floating-point class (fclass), and floating-point approximation
(frcpa, frsqrta) instructions are special cases. These instructions read general or
floating-point registers and write one or two predicate registers.
Volume 1, Part 1: Application Programming Model
"Representation of Values in Floating-point Registers"
for details).
1:88.) Other speculative instructions
1:61