Altera Debug Master Endpoint; Optional Reconfiguration Logic - Intel Cyclone 10 GX User Manual

6.15.1. Altera Debug Master Endpoint

The ADME is a JTAG-based Avalon Memory-Mapped (Avalon-MM) master that provides
access to the transceiver and PLL registers through the system console. You can
enable ADME using the Enable Altera Debug Master Endpoint option available
under the Dynamic Reconfiguration tab in the Native PHY and PLL IP cores. When
using ADME, the Quartus Prime software inserts the debug interconnect fabric to
connect with USB, JTAG, or other net hosts. Select the Share Reconfiguration
Interface parameter when the Native PHY IP instance has more than one channel.
When you enable ADME in your design, you must
• connect an Avalon-MM master to the reconfiguration interface.
•
OR connect the,
reconfig_read
reconfiguration interface. If the reconfiguration interface signals are not connected
appropriately, there will be no clock or reset for the ADME and ADME will not
function as expected.

6.15.2. Optional Reconfiguration Logic

The Cyclone 10 GX Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores
contain soft logic for debug purposes known as the Optional Reconfiguration Logic.
This soft logic provides a set of registers that enable you to determine the state of the
Native PHY and PLL IP cores.
You can enable the following optional reconfiguration logic options in the transceiver
Native PHY and PLL IP cores:
• Capability registers
• Control and status registers
• PRBS soft accumulators (Native PHY IP core only)
6.15.2.1. Capability Registers
The capability registers provide high level information about the transceiver channel
and PLL configuration.
The capability registers capture a set of chosen capabilities of the PHY that cannot be
reconfigured. The following capability registers are available for the Native PHY IP
core.
Table 195. Capability Registers for the Native PHY IP Core
Address
0x200[7:0]
0x204[0]
0x205[0]
0x210[7:0]
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
354
reconfig_reset
,
reconfig_address
Type Name
RO IP Identifier
RO Status Register Enabled
RO Control Register Enabled
RO Number of Channels
6. Reconfiguration Interface and Dynamic Reconfiguration
signals and ground the
and
reconfig_write
Unique identifier for the Native PHY IP instance.
Indicates whether the status registers have been
enabled. 1'b1 indicates that the status registers are
enabled.
Indicates whether the control registers have been
enabled. 1'b1 indicates that the control registers are
enabled.
Shows the number of channels specified for the
Native PHY IP instance.
UG-20070 | 2018.09.24
,
reconfig_write
data signals of the
Description
continued...
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