Enhanced Pcs Ports - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24

2.4.9. Enhanced PCS Ports

Figure 13. Enhanced PCS Interfaces
The labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals.
tx_cal_busy
rx_cal_busy
Serial Data
Clocks
Optional Ports
tx_serial_clk0
(from TX PLL)
Serial Data
Optional Ports
CDR Control
In the following tables, the variables represent these parameters:
• <n>—The number of lanes
• <d>—The serialization factor
• <s>— The symbol size
• <p>—The number of PLLs
Table 43. Enhanced TX PCS: Parallel Data, Control, and Clocks
Name
tx_parallel_data[
<n>128-1:0]
Send Feedback
Cyclone 10 Transceiver Native PHY
Nios Hard
Calibration IP
TX PMA
Serializer
Clock
Generation
Block
RX PMA
CDR Deserializer
Clocks
PRBS
Bitslip
Direction Clock Domain
Input Synchronous to
the clock driving
the write side of
the FIFO
(
tx_coreclkin
or )
tx_clkout
Reconfiguration
Registers
TX Enhanced PCS
RX Enhanced PCS
Description
TX parallel data inputs from the FPGA fabric to the TX PCS. If
you select Enable simplified interface in the Transceiver
Native PHY IP Parameter Editor,
includes only the bits required for the configuration you specify.
You must ground the data pins that are not active. For single
width configuration, the following bits are active:
• 32-bit FPGA fabric to PCS interface width:
tx_parallel_data[31:0]. Ground [127:32].
• 40-bit FPGA fabric to PCS interface width:
tx_parallel_data[39:0]. Ground [127:40].
• 64-bit FPGA fabric to PCS interface width:
tx_parallel_data[63:0] Ground [127:64].
® ®
Intel Cyclone
reconfig_reset
reconfig_clk
reconfig_avmm
TX Parallel Data, Control, Clocks
Enhanced PCS TX FIFO
Interlaken Frame Generator
tx_analog_reset
rx_analog_reset
RX Parallel Data, Control, Clocks
Enhanced PCS RX FIFO
Interlaken Frame Synchronizer
10GBASE-R BER Checker
Bitslip
tx_parallel_data
continued...
10 GX Transceiver PHY User Guide
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