Xaui Phy Ip Core; Acronyms - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Table 115. Avalon-MM Interface Signals
Signal Name
csr_address
csr_read
csr_readdata
csr_write
csr_writedata
csr_waitrequest

2.6.4. XAUI PHY IP Core

Information about this IP core will be available in a future release of this user guide.

2.6.5. Acronyms

Table 116. Ethernet Acronyms
Acronym
AN
BER
DME
FEC
GMII
KR
LD
LT
LP
Send Feedback
Direction
Input
Input
Output
Input
Input
Output
Auto-Negotiation in Ethernet as described in Clause 73 of IEEE 802.3ap-2007.
Bit Error Rate.
Differential Manchester Encoding.
Forward error correction.
Gigabit Media Independent Interface.
Short hand notation for Backplane Ethernet with 64b/66b encoding.
Local Device.
Link training in backplane Ethernet Clause 72 for 10GBASE-KR and 40GBASE-KR4.
Link partner, to which the LD is connected.
Width
11 Use this bus to specify the register address to read
from or write to. The width is:
• 11 bits for 10M/100M/1G/2.5G/5G/10G
(USXGMII) configurations.
1 Assert this signal to request a read operation.
32 Data read from the specified register. The data is
valid only when the
deasserted. The width is:
• 32 bits for 10M/100M/1G/2.5G/5G/10G
(USXGMII) configurations. The upper 16 bits
are reserved.
1 Assert this signal to request a write operation.
32 Data to be written to the specified register. The
data is written only when the
signal is deasserted. The width is:
• 32 bits for 10M/100M/1G/2.5G/5G/10G
(USXGMII) configurations. The upper 16 bits
are reserved.
1 When asserted, indicates that the PHY is busy and
not ready to accept any read or write requests.
• When you have requested for a read or write,
keep the control signals to the Avalon-MM
interface constant while this signal is asserted.
The request is complete when it is deasserted.
• This signal can be high or low during idle cycles
and reset. Therefore, the user application must
not make any assumption of its assertion state
during these periods.
Definition
®
Intel Cyclone
Description
signal is
csr_waitrequest
csr_waitrequest
continued...
®
10 GX Transceiver PHY User Guide
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