Intel Cyclone 10 GX User Manual page 52

Name
rx_set_locktodata[
<n>-1:0]
rx_set_locktoref[<
n>-1:0]
rx_seriallpbken[<n
>-1:0]
rx_prbs_done[<n>-1
:0]
rx_prbs_err[<n>-1:
0]
rx_prbs_err_clr[<n
>-1:0]
Table 41. Calibration Status Ports
Name
tx_cal_busy[<n>-1:0]
rx_cal_busy[<n>-1:0]
Table 42. Reset Ports
Name
tx_analogreset[<n>-1:
0]
tx_digitalreset[<n>-1
:0]
rx_analogreset[<n>-1:
0]
rx_digitalreset[<n>-1
:0]
(20)
Although the reset ports are not synchronous to any clock domain, Intel recommends that you
synchronize the reset ports with the system clock.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
52
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Direction Clock Domain
Input Asynchronous
Input Asynchronous
Input Asynchronous
Output
rx_coreclkin
or
rx_clkout
Output
rx_coreclkin
or
rx_clkout
Input
rx_coreclkin
or
rx_clkout
Direction Clock Domain
Output Asynchronous
Output Asynchronous
Direction Clock Domain
Input Asynchronous
Input Asynchronous
Input Asynchronous
Input Asynchronous
Description
This port provides manual control of the RX CDR circuitry.
This port provides manual control of the RX CDR circuitry.
This port is available if you turn on Enable rx_ seriallpbken
port in the Transceiver Native PHY IP core Parameter Editor.
The assertion of this signal enables the TX to RX serial
loopback path within the transceiver. This signal is enabled in
Duplex or Simplex mode. If enabled in Simplex mode, you
must drive the signal on both the TX and RX instances from
the same source. Otherwise the design fails compilation.
When asserted, indicates the verifier has aligned and captured
consecutive PRBS patterns and the first pass through a
polynomial is complete.
When asserted, indicates an error only after the
signal has been asserted. This signal gets
rx_prbs_done
asserted for three parallel clock cycles for every error that
occurs. Errors can only occur once per word.
When asserted, clears the PRBS pattern and deasserts the
signal.
rx_prbs_done
When asserted, indicates that the initial TX
calibration is in progress. For both initial and
manual recalibration, this signal will be asserted
during calibration and will deassert after
calibration is completed. You must hold the
channel in reset until calibration completes.
When asserted, indicates that the initial RX
calibration is in progress. For both initial and
manual recalibration, this signal will be asserted
during calibration and will deassert after
calibration is completed.
(20)
Resets the analog TX portion of the transceiver
PHY.
Resets the digital TX portion of the transceiver
PHY.
Resets the analog RX portion of the transceiver
PHY.
Resets the digital RX portion of the transceiver
PHY.
UG-20070 | 2018.09.24
Description
Description
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