Intel Cyclone 10 GX User Manual page 68

Figure 15. Directory Structure for Generated Files
The following table describes the directories and the most important files for the
parameterized Transceiver Native PHY IP core and the simulation environment. These
files are in clear text.
Table 68. Transceiver Native PHY Files and Directories
<project_dir>
<your_ip_name> .v or .vhd
<your_ip_name> .qip
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Intel Cyclone 10 GX Transceiver PHY User Guide
68
<Project Directory>
<your_ip_or_system_name>.qsys - Top-level IP variation file
<your_ip_or_system_name>.sopcinfo
<your_ip_name> - IP core variation files
<your_ip_name>.cmp - VHDL component declaration file
<your_ip_name>_bb - Verilog HDL black-box EDA synthesis file
<your_ip_name>_inst - IP instantiation template file
<your_ip_name>.ppf - XML I/O pin information file
<your_ip_name>.qip - Lists IP synthesis files
<your_ip_name>.sip - Lists files for simulation
<your_ip_name>.v or .vhd - Greybox timing netlist
sim - IP simulation files
synth - IP synthesis files
<IP subcore> - IP subcore files
File Name
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
<your_ip_name>.v or .vhd - Top-level simulation file
aldec- Simulator setup scripts
cadence - Simulator setup scripts
mentor - Simulator setup scripts
synopsys - Simulator setup scripts
<your_ip_name>.v or .vhd - Top-level IP synthesis file
sim
<HDL files>
synth
<HDL files>
The top-level project directory.
The top-level design file.
A list of all files necessary for Quartus Prime compilation.
UG-20070 | 2018.09.24
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