Intel Cyclone 10 GX User Manual page 84

Enable RX/TX FIFO double-width mode
TX FIFO mode
TX FIFO partially full threshold
TX FIFO partially empty threshold
Enable tx_enh_fifo_full port
Enable tx_enh_fifo_pfull port
Enable tx_enh_fifo_empty port
Enable tx_enh_fifo_pempty port
RX FIFO mode
RX FIFO partially full threshold
RX FIFO partially empty threshold
Enable RX FIFO alignment word deletion (Interlaken)
Enable RX FIFO control word deletion (Interlaken)
Enable rx_enh_data_valid port
Enable rx_enh_fifo_full port
Enable rx_enh_fifo_pfull port
Enable rx_enh_fifo_empty port
Enable rx_enh_fifo_pempty port
Enable rx_enh_fifo_del port (10GBASE-R)
Enable rx_enh_fifo_insert port (10GBASE-R)
Enable rx_enh_fifo_rd_en port
Enable rx_enh_fifo_align_val port (Interlaken)
Enable rx_enh_fifo_align_clr port (Interlaken)
Table 73. Interlaken Frame Generator Parameters
Enable Interlaken frame generator
Frame generator metaframe length
Enable frame generator burst control
Enable tx_enh_frame port
Enable tx_enh_frame_diag_status port
Enable tx_enh_frame_burst_en port
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Intel Cyclone 10 GX Transceiver PHY User Guide
84
Parameter
Parameter
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Off
Interlaken
8 to 15
1 to 8
On / Off
On / Off
On / Off
On / Off
Interlaken
from 10-29 (no less than pempty_threshold+8)
2 to 10
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
Off
Off
On
On / Off
On
On
5 to 8192 (Intel recommends a minimum metaframe
length of 128)
On
On
On
On
UG-20070 | 2018.09.24
Value
Value
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