Intel Cyclone 10 GX User Manual page 76

Figure 22. TX Soft Bonding Flow
The following figure shows that after deasserting
logic starts filling the TX FIFO until all lanes are full.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
76
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Exit from
tx_digitalreset
Deassert all lanes tx_enh_frame_burst_en
Assert all lanes tx_enh_data_valid
All lanes
full?
yes
Deassert all lanes
tx_enh_data_valid
Any lane
no
send new frame?
tx_enh_frame
asserted?
yes
Wait for extra 16
tx_coreclkin cycles
no
All lanes
full?
yes
TX FIFO pre-fill
completed
tx_digitalreset
UG-20070 | 2018.09.24
no
, TX soft bonding
Send Feedback