Intel Cyclone 10 GX User Manual page 110

Table 103. Resource Utilization
Device
Intel Cyclone 10 GX
2.6.3.2. Using the IP Core
The Intel FPGA IP Library is installed as part of the Intel Quartus Prime Pro Edition
installation process. You can select the 1G/2.5G/5G/10G Multi-rate Ethernet Intel
FPGA IP core from the library and parameterize it using the IP parameter editor.
2.6.3.2.1. Parameter Settings
You customize the PHY IP core by specifying the parameters in the parameter editor in
the Intel Quartus Prime software. The parameter editor enables only the parameters
that are applicable to the selected speed.
Table 104. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Parameters
Name
Speed
Enable IEEE 1588 Precision
Time Protocol
Connect to MGBASE-T PHY
Connect to NBASE-T PHY
PHY ID (32 bit)
Reference clock frequency for
10 GbE (MHz)
Selected TX PMA local clock
division factor for 1 GbE
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
110
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Speed
10M/100M/1G/
2.5G/5G/10G
(USXGMII)
Value
10M/100M/1G/
2.5G/5G/10G
On, Off
On, Off
On, Off
32-bit value
322.265625, 644.53125
, , ,
1 2 4 8
ALMs ALUTs
700 950
The operating speed of the PHY.
Select this option for the PHY to provide latency
information to the MAC. The MAC requires this
information if it enables the IEEE 1588v2 feature.
This option is enabled only for 2.5G and 1G/2.5G.
Note: This option is not available for Intel Cyclone 10
GX devices.
Select this option when the external PHY is MGBASE-T
compatible.
This parameter is enabled for 2.5G, 1G/2.5G, and 1G/
2.5G/10G (MGBASE-T) modes.
Note: This option is not available for Intel Cyclone 10
GX devices.
Select this option when the external PHY is NBASE-T
compatible.
This parameter is enabled for 10M/100M/1G/
2.5G/5G/10G (USXGMII) modes.
An optional 32-bit unique identifier:
• Bits 3 to 24 of the Organizationally Unique Identifier
(OUI) assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value, which is
0x00000000.
Note: This option is not available for Intel Cyclone 10
GX devices.
Specify the frequency of the reference clock for 10GbE.
This parameter is the local clock division factor in the 1G
mode. It is directly mapped to the Native PHY IP Core
GUI options.
UG-20070 | 2018.09.24
Logic Registers Memory Block
(M20K)
1750 3
Description
continued...
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