Intel Stratix 10 User Manual
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Intel Stratix 10 User Manual

E-tile transceiver phy
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UG-20056 | 2019.02.04
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Summary of Contents for Intel Stratix 10

  • Page 1 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Subscribe UG-20056 | 2019.02.04 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    2.2.8. Dynamic Reconfiguration Parameters............46 2.2.9. Port Information..................49 2.2.10. PLL Mode....................52 2.3. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices Revision History..54 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture............. 56 3.1. Physical Medium Attachment (PMA) Architecture............57 3.1.1.
  • Page 3 6. Resetting Transceiver Channels.................. 100 6.1. When Is Reset Required?..................100 6.2. How Do I Reset?....................100 6.2.1. Resetting the Intel Stratix 10 E-Tile Transceiver..........101 6.2.2. Selecting the Reset Controller's Clock Source..........102 6.3. Reset Block Architecture..................102 6.4. PMA Analog Reset....................104 6.5.
  • Page 4 9.2.20. 0x0126: Read Receiver Tuning Parameters..........182 9.2.21. Reading and Writing PMA Analog Parameters Using Attributes.....182 9.3. PMA Registers 0x200 to 0x203 Usage..............184 9.3.1. PMA Analog Reset.................. 186 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 5 B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation..........214 B.1. Building Blocks and Considerations............... 214 B.2. Starting a New Intel Quartus Prime Pro Edition Design..........218 B.3. Selecting the Configuration Clock Source...............219 B.4. Instantiating the Transceiver Native PHY IP............220 B.5.
  • Page 6 Contents B.8. Bringing up the Board..................226 B.9. Debug Tools...................... 227 B.9.1. Monitoring Transceiver Signals..............227 B.10. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation Revision History....228 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 7: Intel ® Stratix ® 10 E-Tile Transceiver Phy Overview

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 8: E-Tile Layout In Stratix 10 Device Variants

    Intel Stratix 10 MX device configurations combine FPGAs with high-bandwidth memory. 1.2.1. Intel Stratix 10 TX H-Tile and E-Tile Configurations Intel Stratix 10 TX FPGAs offer transceiver capability by combining H-Tiles and E-Tiles. This section lists all possible TX FPGA configurations. Figure 1.
  • Page 9 (24 Channels) ® H-Tile E-Tile (24 Channels) (24 Channels) Core Fabric There is no package migration between Intel Stratix 10 GX/SX and Intel Stratix 10 TX device families (H-Tile and E-Tile). ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide...

  • Page 10: Stratix 10 Mx H-Tile And E-Tile Configurations

    1.3. Transceiver Counts in Stratix 10 TX/MX Devices Table 3. Transceiver Counts in Intel Stratix 10 TX Devices with E-Tiles (NF43, SF50, UF50, YF55) The number in the Intel Stratix 10 TX Device Name column indicates the device's Logic Element (LE) count (in thousands LEs). F1760 F2397...

  • Page 11: E-Tile Building Blocks

    10 E-Tile Transceiver PHY Overview UG-20056 | 2019.02.04 Table 4. Transceiver Counts in Intel Stratix 10 MX Devices with E-Tiles (UF55) The number in the Intel Stratix 10 MX Device Name column indicates the device's Logic Element (LE) count (in thousands LEs). F2912 UF55...

  • Page 12: Gxe Transceiver Channel

    This FEC block cannot be used in in aggregate mode with EHIP_CORE because there is no EHIP_CORE in this location. 1.4.1. GXE Transceiver Channel The Intel Stratix 10 E-Tile offers 24 full-duplex transceiver channels. These channels provide continuous data rates from 1 Gbps to 30 Gbps in NRZ mode, and 2 Gbps to 57.8 Gbps in PAM4 mode.

  • Page 13: Gxe Channel Usage

    ® ® 1. Intel Stratix 10 E-Tile Transceiver PHY Overview UG-20056 | 2019.02.04 The Physical Medium Attachment (PMA) provides interfacing capabilities to the following physical channels. • Transmitter (TX) • Receiver (RX) • High speed clocking resources Within a tile, you can configure channels as both bonded and non-bonded in duplex operation.
  • Page 14 ® ® 1. Intel Stratix 10 E-Tile Transceiver PHY Overview UG-20056 | 2019.02.04 Figure 7. GXE Channel Usage Example: Channels Running at Data Rates > 30 Gbps PAM4 PMA Direct Mode without RS-FEC 12 even-numbered channels are available in a tile when the data rate is greater than 30 Gbps.

  • Page 15: Reference Clocks

    You can configure the pins as either 2.5-V LVPECL compliant or 3.3-V LVPECL tolerant. Intel recommends that you use the default setting, which includes source termination at 2.5 V and AC coupling caps. The Intel Stratix 10 Device Datasheet provides the electrical characteristics under the E-Tile section. Additional important electrical information is available in the Intel Stratix 10 GX, MX, and SX Device Family Pin Connection Guidelines.
  • Page 16 The only requirement is that you meet the LVPECL specifications. The Intel Stratix 10 Device Datasheet provides additional electrical characteristics under the E-Tile section. The Intel Stratix 10 GX, MX, and SX Device Family Pin Connection Guidelines also contains additional electrical characteristics .
  • Page 17 ® ® 1. Intel Stratix 10 E-Tile Transceiver PHY Overview UG-20056 | 2019.02.04 Figure 10. Reference Clock Access Transceiver refclk_in_A Transmitter refclk_in_B Receiver Channels 23 to 0 Transceiver refclk_in_A Transmitter Receiver refclk_in_B Reference clock network within an E-Tile Nine REFCLK LVPECL Pins...
  • Page 18 ® ® 1. Intel Stratix 10 E-Tile Transceiver PHY Overview UG-20056 | 2019.02.04 Figure 11. Single Reference Clock Used Across two E-Tiles Transceiver Tile 3 Transmitter Receiver Transceiver Transmitter Receiver REFCLK_0 - Divide Divide LVPECL by 2 Divide LVPECL by 2...

  • Page 19: Ethernet Hard Ip (Ehip)

    The Ethernet Hard IP is a hardened core of assorted multi-lane and single-lane Ethernet components. Intel Stratix 10 E-Tiles include four instances of the Ethernet Hard IP, which in turn supports up to four multi-lane Ethernet MAC stacks, or 24 channels of single-lane Ethernet channel (MAC/PCS) support.
  • Page 20 Channels: 0, 1, 2, 3, 4, 5 Protocol: 25GbE EHIP_LANE RS-FEC: Yes (528, 514) - Fractured The Intel Stratix 10 E-Tile implementation of the Ethernet Hard IP provides the following features and support: • 4x hardened MACs per Intel Stratix 10 E-Tile •...

  • Page 21: Supported Applications/Modes

    ® ® 1. Intel Stratix 10 E-Tile Transceiver PHY Overview UG-20056 | 2019.02.04 1.4.5. Supported Applications/Modes Table 6. Supported Applications/Modes Supported EHIP_CORE EHIP_LANE PMA Direct RS-FEC Dual Mode PAM4/NRZ Application/Mode 100GbE (4 x 25G) – Yes (Aggregate) NRZ w/ FEC 100GbE (2 x 50G) –...

  • Page 22: Intel Stratix 10 E-Tile Transceiver Phy Overview Revision History

    Updated figures in "Intel Stratix 10 TX H-Tile and E-Tile Configurations". • Updated "Transceiver Counts in Intel Stratix 10 TX Devices with E-Tiles (NF43, SF50, UF50, YF55)." • Updated "Transceiver Counts in Intel Stratix 10 MX Devices with E-Tiles (UF55)."...
  • Page 23 ® ® 1. Intel Stratix 10 E-Tile Transceiver PHY Overview UG-20056 | 2019.02.04 Document Changes Version • Updated the "GXE Channel Usage Example: Channels Running at Datarates > 30 Gbps PAM4PMA Direct Mode without RS-FEC" figure • Updated the "GXE Channel Usage Example: Channels Running at Datarates < 30 GbpsPAM4/NRZ PMA Direct Mode without RS-FEC"...

  • Page 24: Implementing The Transceiver Phy Layer In Intel Stratix 10 Devices

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 25: E-Tile Native Phy Ip Core

    Compile Design Verify Design Functionality 2.1.1. E-Tile Native PHY IP Core Much like the Intel Stratix 10 L- and H-Tile Native PHY IP Core, you have multiple options when instantiating the IP: • Instantiating the Native PHY IP to interface to your own IP •...
  • Page 26 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Use the Native PHY IP core in the Intel Quartus Prime Pro Edition software to configure the transceiver PHY for your protocol implementation. To instantiate the IP: 1.

  • Page 27: General And Datapath Parameters

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Figure 15. Native PHY IP Core Parameter Editor Note: Although the Intel Quartus Prime Pro Edition software provides legality checks, the supported FPGA fabric to transceiver interface widths and the supported data rates are pending characterization.
  • Page 28 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 In the Parameter Editor, the parameters are organized in the following sections for each functional block and feature: • General, Datapath Options, and Common PMA Options •...

  • Page 29: Pma Parameters

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Parameter Value Description • TX/RX Duplex: Specifies a single channel that supports both transmission and reception. The default is TX/RX Duplex. Number of data channels 1-24 Specifies the number of transceiver channels you want to implement.
  • Page 30 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 2.2.2.1. TX PMA Options Figure 17. TX PMA Options Table 9. TX PMA Options Parameter Value Description TX PMA modulation type Select the TX PMA modulation type based on your usage.
  • Page 31 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Related Information TX PMA Bonding on page 77 2.2.2.2. TX PMA Pre-equalization Table 10. TX PMA Pre-equalization Parameter Value Description Attenuation For PAM4, 0 to This is the range of attenuation.
  • Page 32 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 2.2.2.3. RX PMA Options Figure 18. RX PMA Options Table 11. RX PMA Options Parameter Value Description RX PMA NRZ, PAM4 Select the RX PMA modulation type based on your usage.

  • Page 33: Core Interface Options

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 2.2.2.4. RX PMA Optional Ports Table 12. RX PMA Optional Ports Parameter Value Description Enable On/Off Enables the optional status output port. This signal rx_is_lockedtodata rx_is_lockedtodata...
  • Page 34 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Figure 19. Core Interface Options 2.2.3.1. Core Interface Parameters The core interface is the interface between the transceiver EMIB and the FPGA core EMIB. You can use these options to customize the core interface.
  • Page 35 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Table 13. Core Interface Parameters Parameter Range Description General Core Interface Options Enable TX fast On/Off Enables the optional fast pipeline registers in the TX parallel datapath. The...

  • Page 36: Pma Interface

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 2.2.3.3. RX Clock Options Table 15. RX Clock Options Parameter Range Description Selected rx_clkout Full-rate, half- Specifies the clock source for the output clock. rx_clkout clock source...

  • Page 37: Pma Adaptation

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 2.2.4.1. PMA Interface Options Table 16. PMA Interface Options Parameter Value Description TX PMA interface 16, 20, 32, 40, Specifies the TX data interface width of the PMA. Refer to PMA Architecture for width mapping the data widths to PMA mode.
  • Page 38 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Figure 21. PMA Adaptation Options Table 17. PMA Adaptation Options Parameter Value Description Enable adaptation On/Off Enables PMA adaptation load soft IP parameter customization. PMA adaptation...
  • Page 39 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Parameter Value Description Fw_default, 0, 1, 2, 3 CTLE Low Frequency Gain Shaping 2. RF_B1 Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8 RF_B1 Setting.
  • Page 40 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Parameter Value Description Same_as_initial_parameter, 0, 1, 2, 3 Puts CTLE Low Frequency Gain Shaping 2. RF_B1 Same_as_initial_parameter, 0, 1, 2, 3, 4, 5, 6, 7, 8 RF_B1 Setting.

  • Page 41: Reed Solomon Forward Error Correction (Rs-Fec) Parameters

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Parameter Value Description RF_P0 Fix/Adaptable Fix, Adaptable Limits RF_P0 - Fix or Adaptable options. RF_P0 Threshold Same_as_initial_parameter, -15, -14, -13, -12, -11, -10, -9, -8, Controls the rate RF_P0 adapts.
  • Page 42 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Table 18. RS-FEC Mode Configurations Supported Mode RS-FEC FEC Mode Alignment/Scrambling/ Transcoder Code Transcoder Mode Bypass Type 32GFC/ CPRI 24G (x1, x2, x3, x4) Fractured Fibre channel...
  • Page 43 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Parameter Value Description RS-FEC block enabled, the RS-FEC lanes used must be contiguous and must fit within a single four-channel RS-FEC block. Alignment/Scrambling/Transcoder Basic Mode Basic Mode selects Ethernet-like mode for a specific lane. The...
  • Page 44 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 2.2.6.2. 128 GFC Mode In the 128 GFC mode, fibre-channel is enabled for all lanes and no additional settings are required. Scrambling or descrambling is disabled in 128 GFC mode. While the transcoder bypass settings options for the RS-FEC are available, they are not required for fibre-channel mode.

  • Page 45: Reset Parameters

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 2.2.6.3. 25 GbE FEC Direct Mode Figure 27. 25 GbE FEC Direct Mode Settings The RS-FEC is enabled in fractured mode. 2.2.6.4. Interlaken Mode The RS-FEC is available in 100G Interlaken mode. In the 100G Interlaken mode, you must set the RS-FEC to aggregate mode across all four lanes with transcoder bypass enabled.

  • Page 46: Dynamic Reconfiguration Parameters

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Figure 28. Reset Options Table 20. Reset Parameters Parameter Value Description Enable manual reset On/Off When enabled, sets manual reset mode. You must control all reset signals for the device.
  • Page 47 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Figure 29. Dynamic Reconfiguration Options Table 21. Dynamic Reconfiguration Parameters Parameter Value Description Enable dynamic reconfiguration On/Off Enables the dynamic reconfiguration interface. Share reconfiguration interface On/Off...
  • Page 48 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Parameter Value Description where 'n' is the log base 2 of the number of channels. Address bits [18:0] provide the register offset address within the reconfiguration space of the selected channel.

  • Page 49: Port Information

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Parameter Value Description Number of reconfiguration 1 - 8 Specifies the number of reconfiguration profiles to support profiles when multiple reconfiguration profiles are enabled. Store current configuration to...
  • Page 50 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Port Name Direction Width Description Output 1 bit for each Ready status signal of the receiver. rx_ready channel Output 1 bit for each Locked to data status signal of the...
  • Page 51 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Port Name Direction Width Description Input 1 bit for each Transfer clock between the FPGA core tx_coreclkin channel and the transmitter Input 1 bit for each...

  • Page 52: Pll Mode

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 E-Tile Native TX/RX PMA Enable TX/RX Valid Parallel Data Note PHY Mode Interface double width Width transfer PMA Direct Data [55:40] Data [55:40] is the first data group. Data [15:0] is the second data group.
  • Page 53 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Figure 30. E-Tile Native PHY PLL Mode Table 24. E-Tile Native PHY PLL Mode Options Parameter Value Description Number of reference clock 1, 2, 3, 4, 5 Specifies the desired number of reference clocks.

  • Page 54: Implementing The Transceiver Phy Layer In Intel Stratix 10 Devices Revision History

    2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Related Information Intel Stratix 10 Device Datasheet 2.3. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices Revision History Document Changes Version 2019.02.04 Made the following changes: •...
  • Page 55 2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG-20056 | 2019.02.04 Document Changes Version • Changed the following parameters in the "General, Datapath Options, and Common PMA Options" table: — Removed the Enable RS-FEC parameter — Removed the Enable datapath and interface reconfiguration parameter —...

  • Page 56: Intel Stratix 10 E-Tile Transceiver Phy Architecture

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 57: Physical Medium Attachment (Pma) Architecture

    This FEC block cannot be used in in aggregate mode with EHIP_CORE because there is no EHIP_CORE in this location. Related Information E-Tile Channel Placement Tool 3.1. Physical Medium Attachment (PMA) Architecture The PMA acts as the analog front end for the Intel Stratix 10 E-Tile transceivers. ® ® Intel...
  • Page 58 The PMA transmitter serializes parallel data, and the PMA receiver deserializes serial data. The Intel Stratix 10 E-Tile PMA GXE channels support both NRZ and PAM4 data formats. A single bit of data is transmitted/received in one UI in NRZ mode, while two bits of data are transmitted/received in one UI in PAM4 mode.

  • Page 59: Transmitter Pma

    3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 dedicated clocking resources. Muxing options allow you to select the desired external reference clock pin to drive the individual clock input ports for each PMA channel. The block diagram below demonstrates the muxing capability.
  • Page 60 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 transmitter and TX buffer are enabled, the TX buffer drives normal differential data, and the differential impedance on both TX and RX lines is in the range of 80 (min), 100 (typ), 120 (max) Ω.
  • Page 61 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 The ATTN/PRE/POST taps can be dynamically changed via the Avalon-MM interface. For more details on PMA attribute support and programming, refer to PMA/PCS Avalon-MM Register Map and PMA Attribute Codes to configure these parameters.
  • Page 62 PHY to debug the PMA without involving the upper protocol stack layers. The Intel Stratix 10 E-Tile has an on-chip pseudo random pattern generation block that operates in all bit modes and can generate several patterns. In addition to this, it can generate an 80-bit user-defined pattern.
  • Page 63 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 For more details on PRBS13Q pattern generation, refer to CEI-56G-VSR-PAM4 specifications. On similar lines, the PRBS31Q pattern is a repeating 2 -1 symbols long, formed by gray coding and PAM4 encoding of the PRBS31 pattern. This pattern is used for receiver testing.

  • Page 64: Receiver Pma

    The transceiver RX is AC-coupled on-chip. Therefore, no off-chip AC-coupling capacitor is required as long as the RX input common mode is between AGND and VCCH_GXE and the RX input amplitude is < 1200 mVp-p differential. For details, refer the Intel Stratix 10 Device Family Pin Connection Guidelines.
  • Page 65 170 • Intel Stratix 10 Device Family Pin Connection Guidelines 3.1.2.1.2. RX Adaptation Modes The Intel Stratix 10 E-Tile supports the initial and continuous adaptation modes. Table 29. Intel Stratix 10 E-Tile Receiver PMA RX Adaptation Modes Mode...
  • Page 66 3.1.2.2. Clock Data Recovery (CDR) Block Clocking resources in the receiver enable the clock data recovery feature in Intel Stratix 10 devices. The CDR block locks to the received signal and extracts the transmitted data sequence by recovering the clocking information from the distorted received signal.
  • Page 67 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 3.1.2.3. Input Sampler The Input Sampler block is responsible for converting the serial input signal into a retimed bit stream using the high-speed serial clock generated by the CDR block.

  • Page 68: Pma Tuning

    User-defined pattern 80-bit 3.1.3. PMA Tuning The Intel Stratix 10 E-Tile PMA supports various data rates and channel configurations to meet the most advanced PAM4 and NRZ protocols across a temperature range. The default adaptation sequence works at a static temperature regardless of the load.
  • Page 69 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Figure 38. Case 2: Dynamic Temperature Ramp The link is brought up with initial adaptation at a static temperature (low). Tuning RX AFE Parameters Will Bridge the Gap Initial Adaptation...
  • Page 70 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Figure 39. STF and DTF Link Bring Up PMA Bring Up PMA Bring Up Static Temperature Flow (STF) Dynamic Temperature Flow (DTF) Start Program the Device Start Configure Hard PRBS...
  • Page 71 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Note: Completion of initial adaptation can be read out by polling the PMA register. For more details refer to the PMA Register Map. Note: During PMA performance verification testing, with continuous adaptation running in background, error bits cannot be accumulated to calculate BER because the Hard PRBS error counter is in a busy state.
  • Page 72 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Figure 40. PMA Tuning Generic Flow Start Tuning for DTF Run STF at temp A & measure the BER at temp B Is the link performance optimum with STF across...
  • Page 73 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Table 32. PMA Parameter Tuning for Optimal Performance These are the tuned PMA parameter settings that result in optimal link performance across a temperature sweep for each test configuration. An integer value means that the parameter is fixed, and "Firmware Default"...

  • Page 74: Loopback Modes

    3.1.4. Loopback modes Loopback modes are DFT features used to verify different blocks of the transceiver PMA. Intel Stratix 10 E-Tile transceivers have loopback modes to debug different blocks of the transceiver. Intel Stratix 10 E-Tile transceivers support the following loopback modes: •...
  • Page 75 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Note: Currently, only the PRBS31/PRBS31Q patterns are supported in internal or serial loopback mode. Figure 41. Internal or Serial Loopback Path TX PMA Error TX Data Injector NRZ/ Gray Encoder/...

  • Page 76: Pma Interface

    3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Figure 42. Reverse Parallel Loopback Path TX PMA Error TX Data Injector NRZ/ Gray Encoder/ Serializer Buffer PAM4 Pre-coder Data Pattern Generator EHIP_LANE/ EHIP_CORE/ TX EQ RS-FEC/ PMA Direct...

  • Page 77: Tx Pma Bonding

    The two TX FIFO modes are elastic or phase compensation. Elastic mode is identical to Basic mode in Intel Stratix 10 L/H-tiles where you can monitor the FIFO full or empty and almost full or empty signals. The control FIFO writes and reads through the read and write enable ports.
  • Page 78 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 There are two mechanisms by which to facilitate bonding: • Transceiver interface deskew logic • Dedicated balanced transceiver reference clock tree Once you enable bonding in the Native PHY IP core, both of these bonding mechanisms are activated.

  • Page 79: Unused Transceiver Channel

    For example, if the pin_name is Pin AB44, structure the per-pin assignment with the following syntax: set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to AB44 3.2. Physical Coding Sublayer (PCS) Architecture The Intel Stratix 10 E-Tile PCS is located in the EHIP_LANE block, which includes the following features: • 64B/66B encoder/decoder •...

  • Page 80: Rs-Fec Modes

    3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 100GbE with KP-FEC uses two physical PAM4 coded lanes, also called, 100 Gigabit Attachment Unit Interface (CAUI-2). It uses the RS(544,514) FEC. The two physical lanes are supported by bit-multiplexing the RS-FEC core’s four PMA lanes pairwise outside of the RS-FEC core.
  • Page 81 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Figure 45. E-Tile Floor Plan Configurations This figure illustrates the placement of various architecture blocks, and the modes supported in the RS-FEC blocks. Note: 1. This block cannot be used in combination with EHIP_CORE - fractured bypass.
  • Page 82 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Figure 46. Datapath Routing for RS-FEC Configurations Supported RS-FEC configurations are shown inTable 37 on page 80. RS-FEC (528, 514) or EHIP_CORE (544, 514) PMA CH11 (100G MAC (Aggregate:...
  • Page 83 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Channels FEC Block Mode FEC Receives Data From 6 to 7 Bypass EHIP_LANE 8 to 9 Fractured EHIP_LANE 10 to 11 Fractured FPGA core Figure 47. Example Channel Configurations Implementing Various FEC Modes using the E-Tile Channel Placement Tool Your implementation could vary depending on your intended application.
  • Page 84 3. Intel Stratix 10 E-Tile Transceiver PHY Architecture UG-20056 | 2019.02.04 Refer to the Intel Stratix 10 E-Tile Channel Placement Tool for details about possible channel placement based on system requirements. Figure 48. Channel Configurations Implementing Various FEC Modes Check Table 38 on page 82 for configuration description.

  • Page 85: Intel Stratix 10 E-Tile Transceiver Phy Architecture Revision History

    Added further description about the absolute maximum transceiver input in the "Programmable Termination Modes" section. • Changed the description for the initial adaptation mode in the "Intel Stratix 10 E-Tile Receiver PMA RX Adaptation Modes" table. • Added a note about the gearbox in the "PMA Interface" section.

  • Page 86: Clock Network

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 87 PMA Analog Reset to reset the internal controller. Refer to the Register Map for more details on attribute codes and data. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 88 4. Clock Network UG-20056 | 2019.02.04 Figure 50. REFCLK LVPECL Pins This diagram illustrates the nine pins and the reference clock network within a given Intel Stratix 10 E- refclk Tile. Transceiver refclk_in_A Transmitter refclk_in_B Receiver Channels 23 to 0...

  • Page 89: Qsf Assignments For Reference Clock Pins

    These use cases provide guidance about how you can connect various clocks through the GUI for different use cases. (10) Refer to the Intel Stratix 10 Device Datasheet for the reference clock voltage rating electrical specifications. (11) Refer to the Intel Stratix 10 Device Datasheet for the reference clock frequency specification.

  • Page 90: Single 25 Gbps Pma Direct Channel (With Fec) Within A Single Fec Block

    (257.8125 MHz) to . If tx_coreclkin rx_clkout rx_coreclkin you use any other source for , make sure tx_coreclkin rx_coreclkin have 0 PPM difference with tx_coreclkin rx_coreclkin tx_clkout , respectively rx_clkout ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 91: Four 25 Gbps Pma Direct Channel (With Fec) Within A Single Fec Block

    An interruption on the master channel PMA, a PMA reset, for example, impacts the slave channels. This creates a dependency between the master and the slave channels. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 92 EMIB clock for each 25 Gbps channel. The FEC clock is still provided by the Master channel. This method removes the dependency of a PMA reset between the ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 93 TX PMA generated parallel clock (line rate / PMA interface width) TX PMA generated parallel clock div by 2 RX PMA generated parallel clock div by 2 RX PMA generated parallel clock (line rate / PMA interface width) ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 94: Pma Direct 25 Gbps X 4 (Fec Off)

    TX PMA generated parallel clock (line rate / PMA interface width) TX PMA generated parallel clock div by 2 RX PMA generated parallel clock div by 2 RX PMA generated parallel clock (line rate / PMA interface width) ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 95: Pma Direct 10.3125 Gbps X 4

    (402.83 MHz) to tx_coreclkin rx_clkout rx_coreclkin If you use any other source for , make sure tx_coreclkin rx_coreclkin have 0 PPM difference with the tx_coreclkin rx_coreclkin tx_clkout , respectively. rx_clkout ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 96 TX PMA generated parallel clock div by 2 RX PMA generated parallel clock div by 2 RX PMA generated parallel clock (line rate / PMA interface width) For clocking within the EHIP, see the E-tile Hard IP for Ethernet Intel FPGA IP User Guide. Related Information E-tile Hard IP for Ethernet Intel FPGA IP User Guide ®...

  • Page 97: Clock Network Revision History

    Changed the maximum reference clock frequency from 500 to 700 and added related instructions to Reference Clock Pins, and clarified that, although the Intel Stratix 10 E-Tile transceiver reference clock input pin supports a frequency range of 125 MHz to 700 MHz, the reference clock network supports a maximum frequency of 500 MHz.

  • Page 98: Pma Calibration

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 99: Pma Calibration Revision History

    • Added instructions to enable/disable the PMA using PMA attribute code 0x0001. • Added the "Changing a Setting When the PMA Cannot be Running" flowchart. 2018.01.31 Initial release. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 100: Resetting Transceiver Channels

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 101: Resetting The Intel Stratix 10 E-Tile Transceiver

    Reset Controller Bypass on page 112 6.2.1. Resetting the Intel Stratix 10 E-Tile Transceiver Use the steps below when both digital and analog resets are needed. Changing the data rate is an example of when both digital and analog resets are needed.

  • Page 102: Selecting The Reset Controller's Clock Source

    6.2.2. Selecting the Reset Controller's Clock Source When you instantiate a Native PHY IP, the software automatically instantiates Master Transceiver Reset Sequencer (TRS) and Local TRS (LTRS) blocks. Use the Intel Quartus Prime Pro Edition assignment settings editor to provide a 25, 100, or 125 MHz...
  • Page 103 Request Acknowledgement Master TRS The Intel Quartus Prime Pro Edition software detects the presence of instantiated transceiver Native PHY IP cores and automatically inserts the TRS. The tx_reset inputs, either generated by you or through the reset controller, are rx_reset received by the Local TRS.

  • Page 104: Pma Analog Reset

    105 • Automatic Reset Mode on page 105 • E-tile Hard IP for Ethernet Intel FPGA IP User Guide 6.4. PMA Analog Reset The transceiver has an internal controller that is clocked by the transceiver's reference clock. Table 46.

  • Page 105: High Level Specification

    Figure 60. Reset Block Diagram with Single Reset Control E-Tile Native PHY IP Reset Controller RS-FEC (Local TRS) reset EMIB tx_ready PMA Interface rx_ready Request Acknowledgement Master TRS ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 106 (if PMA is reset/configured) rx_is_lockedtodata rx_ready Note: 1. If you used the AVMM bus to reconfigure the RS-FEC/EMIB/PMAIF, you must assert rx_reset until the RS-FEC/EMIB/PMAIF registers are written. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 107: Manual Reset Mode

    Output from the PMA indicating the PMA is ready. This must be asserted before tx_pma_ready asserting or deasserting any TX resets. , and ports do not appear in manual reset mode. reset rx_ready tx_ready ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 108 112 for TX and RX reset sequences. 4. You deassert the signal after resetting the blocks. reset_req 5. The Master TRS sees the deasserted and deasserts the reset_req reset_ack output. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 109 (1) rx_reset_ack rx_aib_reset rx_transfer_ready rx_pmaif_reset Min 100 ns rx_rsfec_reset Note: 1. If you have enabled the RS-FEC block, you must assert rx_reset_req after the tx_transfer_ready output is asserted. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 110 (1) rx_reset_ack rx_aib_reset rx_transfer_ready rx_pmaif_reset Min 100 ns rx_rsfec_reset Note: 1. If you have enabled the RS-FEC block, you must assert rx_reset_req after the tx_transfer_ready output is asserted. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 111 AVMM Reset and reconfigure PMA using PMA attribute codes Note: 1. If you have enabled the RS-FEC block, you must assert rx_reset_req after the tx_transfer_ready output is asserted. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 112: Reset Controller Bypass

    A. Do not assert the rx_ready tx_reset_req on instance B. rx_reset_req 6.5.3.1. Reset Controller Bypass Ports You can control the reset signals listed in the following table. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 113 Because the RS-FEC is enabled, you must complete the TX reset on a specific channel before resetting the RX on that channel. Ensure the PMA is ready before asserting or deasserting reset to the individual transceiver digital blocks. Ensure the ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 114: Intel Quartus Prime Instantiated Transceiver Reset Sequencer

    PMA attribute codes 6.6. Intel Quartus Prime Instantiated Transceiver Reset Sequencer Intel Quartus Prime auto-infers the Master TRS during synthesis and auto-connects the Master TRS to the Local TRS using the debug fabric master end-point to slave end- point auto-connect technology.

  • Page 115: Block Diagrams

    Per Channel is Turned ON and Enable Individual TX and RX Reset is Turned E-Tile Native PHY IP Reset Controller [0] reset[0] tx_ready[0] rx_ready[0] Reset Controller [N] reset[N] tx_ready[N] rx_ready[N] ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 116 Reset Controller when Use Separate TX/RX Reset Per Channel is Turned OFF and Enable Individual TX and RX Reset is Turned OFF E-Tile Native PHY IP Reset Controller reset[0] reset[N:1] tx_ready[N:0] rx_ready[N:0] ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 117: Interfaces

    Asserts a few clock cycles after deassertion of TX resets. Output Number of Status signal to indicate when RX resets sequencing is complete. rx_ready channels Deasserts during RX reset assertion. continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 118: Resetting Transceiver Channels Revision History

    Added the "Enable individual TX and RX reset" Reset Parameter. • Removed references to the sequencer. • Moved the "Resetting the Intel Stratix 10 E-Tile Transceiver" task and re-wrote it to encompass both analog and digital reset procedures. • Restructured "Automatic Reset Mode."...

  • Page 119: Dynamic Reconfiguration

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 120: Dynamically Reconfiguring Channel Blocks

    AVMM master. Because each channel has its own dedicated AVMM interface, you can dynamically reconfigure channels either concurrently or sequentially, depending on how the AVMM master is connected to the AVMM reconfiguration interface. Figure 78. Reconfiguration Interface in Intel Stratix 10 Transceiver IP Cores Native PHY IP Core AVMM Master Ch0: AVMM...

  • Page 121: Unsupported Features

    Non RS-FEC to RS-FEC reconfiguration 7.4. Reading from the Dynamic Reconfiguration Interface Reading from the reconfiguration interface of the Transceiver Native PHY IP core retrieves the current value at a specific address. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 122: Writing To The Dynamic Reconfiguration Interface

    All writes to the reconfiguration interface must be read-modify-writes, because two or more features may share the same reconfiguration address. You need to monitor the signal. reconfig_waitrequest ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 123: Multiple Reconfiguration Profiles

    For example, the configuration file for Profile 0 is stored as . The Intel Quartus <filename_CFG0.sv> Prime Timing Analyzer includes the necessary timing paths for all configurations based on initial and target profiles. You can also generate full reconfiguration files or reduced configuration files that contain only the attributes that differ between the multiple configured profiles.

  • Page 124: Reconfiguration Files

    UG-20056 | 2019.02.04 7.6.1. Reconfiguration Files The Intel Stratix 10 E-Tile Transceiver Native PHY IP core optionally allows you to save the parameters you specify for the IP instances as configuration files. The configuration file stores addresses and data values for that specific IP instance. The configuration files are generated during IP generation.

  • Page 125: Embedded Reconfiguration Streamer

    • Bit[7] equal to 1 to launch the reconfiguration streamer 2. Continue to read register 0x40141[0] until it becomes 0 to indicate that the reconfiguration streamer is finished. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 126: Arbitration

    If you do not reconfig_writedata connect the reconfiguration interface signals appropriately, the ADME does not function properly. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 127: Recommendations For Pma Dynamic Reconfiguration

    Some PMA features that can be dynamically reconfigured, like the reference clock source, the TX and RX datarate require the PMA and digital blocks to be in the reset state. Intel recommends that you: • Hold the channel transmitter in digital reset and assert PMA attribute codes to disable the PMA TX during reconfiguration.
  • Page 128 Wait for tx/rx_reset_ack asserts Deassert the EMIB/RS-FEC/PMAIF resets in the sequence indicated in the manual reset section of the reset chapter Related Information PMA Attribute Codes on page 170 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 129: Pma Attribute Details

    You can use the reconfiguration interface on the channel instance to specify which reference clock source drives the transmitter, the receiver, or both. The channel supports clocking up to five different reference clock sources. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 130 0x91[0] to restore the previous profile. You must clear register 0x8A[7] by writing 0x8A[7] to 1 before sending any attributes to the PMA. Related Information Resetting Transceiver Channels on page 100 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 131: Ports And Parameters

    Asynchronous assertion and synchronous deassertion. Input Write enable signal. Signal reconfig_write reconfig_clk is active high. Input Read enable signal. Signal reconfig_read reconfig_clk is active high. continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 132 ..., reconfig_address_ch0[18:0] address reconfig_writedata_ch3[7:0], ..., reconfig_writedata_ch0[7:0] writedata reconfig_readdata_ch3[7:0], ..., reconfig_readdata_ch0[7:0] readdata reconfig_waitrequest_ch3, ..., reconfig_waitrequest_ch0 waitrequest Note: The RS-FEC reconfiguration interface will not be separated for each channel. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 133 Native PHY. You can access certain test and debug functions using System Console with the ADME. Refer to the "Embedded Debug Features" section for more details about ADME. continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 134 Store current configuration to profile specified. Load configuration from selected profile Loads the current Native PHY parameter settings to the profile specified by Store current configuration to profile specified. continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 135: Embedded Debug Features

    Store current configuration to profile parameter and then stores the parameters back to the profile. 7.13. Embedded Debug Features The Intel Stratix 10 Transceiver Native PHY IP cores provide the following optional debug features to facilitate embedded test and debug capability: •...

  • Page 136: Optional Dynamic Reconfiguration Logic

    UG-20056 | 2019.02.04 7.13.2. Optional Dynamic Reconfiguration Logic The Intel Stratix 10 Transceiver Native PHY IP cores contain soft logic for debug purposes known as the Optional Reconfiguration Logic. This soft logic provides a set of registers that enable you to determine the state of the Native PHY IP cores.

  • Page 137: Transceiver Register Map

    The bit self-clears. 5. Check register 0x204[0]. A '0' indicates the loading was successful. Related Information Loading Parameters into the Receiver on page 183 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 138: Alternative Method For Setting Pma Attributes

    Made the following changes: • Changed some descriptions in the "Dynamic Reconfiguration" section. • Added a feature to the "Intel Stratix 10 Dynamic Reconfiguration Feature Support" table. • Updated the reconfig_write waveform in the "Writing to the Reconfiguration Interface" figure. •...
  • Page 139 Removed reference to the PMA register read/write sequencer for this release pending testing in the "Changing Analog PMA Settings" section. • Updated the address, writedata, and readdata bus widths in the "Ports and Parameters" and "ADME" sections. 2018.01.31 Initial release. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 140: Dynamic Reconfiguration Examples

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 141 10. Change to internal or serial loopback mode by using PMA attribute code 0x0008. a. Write 0x84[7:0] = 0x01. b. Write 0x85[7:0] = 0x01. Write 0x86[7:0] = 0x08. d. Write 0x87[7:0] = 0x00. e. Write 0x90[0] = 1’b1. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 142 15. Disable internal or serial loopback mode by using PMA attribute code 0x0008. a. Write 0x84[7:0] = 0x00. b. Write 0x85[7:0] = 0x00. Write 0x86[7:0] = 0x08. d. Write 0x87[7:0] = 0x00. e. Write 0x90[0] = 1’b1. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 143: Prbs Usage Model

    PRBS Control PMA Attribute Code Definition, PMA Attribute Code 0x02, PRBS Enable Address Direction Definition 3'b000: prbs7 3'b001: prbs9 3'b010: prbs11 0x84[2:0] input 3'b011: prbs15 3'b100: prbs23 3'b101: prbs31 3'b110: prbs13 continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 144 Read 0x8B[0] until it changes to 0. h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value. 3. Enable the transceiver channel if it is not running already. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 145 Read 0x8B[0] until it changes to 0. h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value. 9. Read the lower 16 bits of the error counter. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 146: Pma Error Injection

    Inject either a single error or a burst of errors on the TX driver output using PMA attribute codes. This switches the internal TX error injection signal on and off for the number of bits requested. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 147: Pma Receiver Equalization Adaptation Usage Model

    8.4. PMA Receiver Equalization Adaptation Usage Model The PMA receiver adaptive equalization engine allows the equalization blocks to adapt to an optimal value. These optimal values can be read back. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 148 2. Configure PMA attribute code 0x01 as following to enable TX and RX: a. Write 0x84[7:0] = 0x07. b. Write 0x85[7:0] = 0x00. Write 0x86[7:0] = 0x01. d. Write 0x87[7:0] = 0x00. e. Write 0x90[0] = 1'b1. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 149 Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value. Note: You can stop continuous adaptation. Refer to Receiver Tuning Controls for more information. Related Information 0x000A: Receiver Tuning Controls on page 175 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 150: User-Defined Pattern Example

    Write 0x86[7:0] = 0x19. d. Write 0x87[7:0] = 0x00. e. Write 0x90[0] = 1’b1. Read 0x8A[7]. It should be 1. g. Read 0x8B[0] until it changes to 0. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 151 Read 0x8A[7]. It should be 1. g. Read 0x8B[0] until it changes to 0. h. Write 0x8A[7] to 1 to clear the 0x8A[7] flag. 9. Load pattern [69:60]. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 152 Write 0x90[0] = 1’b1. Read 0x8A[7]. It should be 1. g. Read 0x8B[0] until it changes to 0. h. Write 0x8A[7] to 1 to clear the 0x8A[7] flag. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 153: Configuring The Attenuation Value (Vod)

    10. Write 0x84[7:0] = 0xEE. 11. Write 0x85[7:0] = 0x80. 12. Write 0x86[7:0] = 0x15. 13. Write 0x87[7:0] = 0x00. 14. Write 0x90[0] = 1’b1. 15. Read 0x8A[7]. It should be 1 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 154: Configuring Pretap1 Values

    5. Write 0x90[0] = 1'b1. 6. Read 0x8A[7]. It should be 1. 7. Read 0x8B[0] until it changes to 0. 8. Write 0x8A[7] to 1 to clear the 0x8A[7] flag. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 155: Configuring A Pma Parameter Tunable By The Adaptive Engine

    10. Write 0x84[7:0] = 0x01. 11. Write 0x85[7:0] = 0x00. 12. Write 0x86[7:0] = 0x6C. 13. Write 0x87[7:0] = 0x00. 14. Write 0x90[0] = 1'b1. 15. Read 0x8A[7]. It should be 1. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 156 Refer to the Register Map for more details. Further information about configuring PMA parameters will be available in a future release of this user guide. Related Information Register Map on page 165 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 157: Configuring A Pma Parameter Using Native Phy Ip

    5. Refer to the "Configuring a PMA Parameter Using Native PHY IP" design example for details. Related Information • PMA Parameters on page 29 • PMA Adaptation on page 37 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 158: Native Phy Ip Gui Details

    PMA across dynamic temperature conditions, PMA parameter tuning is required before initiating receiver initial adaptation and receiver continuous adaptation. What follows is the Native PHY IP GUI configuration flow. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 159 802.3bs/bj specifications. If you have a different test setup, you must tune some of the parameters to achieve the optimal performance across the PVT. 4. Initial adaptation and continuous adaptation PMA parameter options are: ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 160 0x200 to 0x203 Usage. You can select the soft registers to choose and load the test configuration. The status of the test configuration load feature can be monitored using rcp_load_finish ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 161 2. Load your PMA configuration, and apply it to all channels. Figure 96. Enable Soft IP GUI To enable the soft IP, turn on Enable dynamic reconfiguration and Enable control and status registers. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 162 Refer to Loading a PMA Configuration for more details. Related Information • PMA Adaptation on page 37 • PMA Bring Up Flow on page 69 • PMA Analog Reset on page 104 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 163: Loading A Pma Configuration

    PMA Registers 0x200 to 0x203 Usage on page 184 • PMA Bring Up Flow on page 69 8.13. Dynamic Reconfiguration Examples Revision History Document Changes Version 2019.02.04 Made the following changes: continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 164 Added the "PMA Receiver Equalization Adaptation Flowchart." • Added the "Equalizer Bits" figure. • Added the "PRBS Bits" figure. • Added error injection instructions to the "PRBS Usage Model" section. 2018.01.31 Initial release. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 165: Register Map

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 166: Pma Control And Status Registers

    Bit is set to: read- Status Bit 0x40141 • 1'b1: streaming is in progress only • 1'b0: streaming is complete 0x40143 Request PMA configuration load read- Configurat write continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 167: Pma Avmm Registers

    RX datapath clock enable Receive full clock out ( ) enable rx_pma_clk Receive half clock out ( ) enable rx_pcs_clk Receive div66 clock out ( ) enable rx_pcs_div66_clk continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 168 Transceiver interface TX FIFO empty threshold 0x14 [7:6] Transceiver interface TX FIFO almost empty threshold [2:0] Transceiver interface TX FIFO almost empty threshold 0x15 [7:4] Transceiver interface TX FIFO full threshold continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 169 Core PMA attribute control 0x81 [7:0] Core PMA attribute control 0x84 [7:0] PMA attribute data 0x85 [7:0] PMA attribute data 0x86 [7:0] PMA attribute code 0x87 [7:0] PMA attribute code continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 170: Pma Attribute Codes

    Use the following attribute codes to set registers 0x87[7:0] down to 0x84[7:0] in the PMA register map to send or receive attribute values to or from the PMA. 9.2.1. 0x0001: PMA Enable/Disable Attribute Code 0x0001 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 171: 0X0002: Pma Prbs Settings

    0x84[3]: 1’b0 • 0x84[4]: Reseed on error • 0x84[5]: Autoseed correct (generator goes from all ‘0’ to all ‘1’) • 0x84[6]: 1’b0 • 0x84[7]: Stop on Error (RX) ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 172: 0X0003: Data Comparison Set Up And Start/Stop

    • 0x85[2:0]: 3'b100 to select as data to be compared against tx_prbs • 0x85[2:0]: 3'b110 to select 20'h00000 as data to be compared against • 0x85[7:3]: 5'h00 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 173: 0X0005: Tx Channel Divide By Ratio

    0x0005: Success Related Information Supported Data Rate Ratios for PMA Attribute Codes 0x0005 and 0x0006 on page 187 9.2.5. 0x0006: RX Channel Divide By Ratio Attribute Code 0x0006 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 174: 0X0008: Internal Or Serial Loopback And Reverse Parallel Loopback Control

    • 0x84[7:5]: 3'h0 • 0x85[0]: 1'b1 to change the internal or serial loopback settings • 0x85[1]: 1'b1 to set the reverse parallel loopback settings • 0x85[7:2]: 6'h00 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 175: 0X000A: Receiver Tuning Controls

    0x84[3:0]: 4'b0110: Run continuous adaptive equalization • 0x84[7:4]: 0x0 • 0x85[7:0]: 0x00 PMA Can Be Running While Updating PMA Attribute? Return Value {0x89[7:0],0x88[7:0]} 0x000A 9.2.8. 0x0011: PMA TX/RX Calibration Attribute Code 0x0011 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 176: 0X0013: Tx/Rx Polarity And Gray Code Encoding

    0x85[2]: 1'b1 to set TX PMA4 MSB/LSB mapping, gray code encoding, precoding to provided values on 0x84[3:1] • 0x85[3]: 1'b1 to set RX PMA4 MSB/LSB mapping, gray code encoding, precoding to provided values on 0x84[7:4] • 0x85[7:4]: 4'h0 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 177: 0X0014: Tx/Rx Width Mode

    0x84[7]: 1'b0 to set RX in NRZ mode • 0x85[7:0]: 8'h00 PMA Can Be Running While Updating PMA Attribute? Return Value {0x89[7:0],0x88[7:0]} 0x0014 9.2.11. 0x0015: TX Equalization Attribute Code 0x0015 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 178: 0X0017: Error Counter Reset

    0x0000 if failed to apply since new EQ setting exceeds limit of allowed EQ 9.2.12. 0x0017: Error Counter Reset Attribute Code 0x0017 Description Resets the error counter. • 0x84[7:0]: 8'h00 • 0x85[7:0]: 8'h00 PMA Can Be Running While Updating PMA Attribute? ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 179: 0X0018: Status/Debug Register

    0x0018 9.2.14. 0x0019: Status/Debug Register Next Write Field Attribute Code 0x0019 Description Writes the next field of a status/debug register. 0x85[7:0], 0x84[7:0] represent the value to be written. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 180: 0X001A: Status/Debug Register Next Read Field

    {0x85[7:0],0x84[7:0]}: — Number of errors to inject PMA Can Be Running While Updating PMA Attribute? Return Value {0x89[7:0],0x88[7:0]} 0x001B 9.2.17. 0x001C: Incoming RX Data Capture Attribute Code 0x001C ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 181: 0X001E: Error Count Status

    0x84[1]: 1'b1: Termination undriven (floating) • 0x84[3:2]: 2'h0 • 0x84[4]: 1'b0: Normal TX behavior (both TX outputs driven to VCC) (default) • 0x84[4]: 1'b1: TX output tristated when disabled ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 182: 0X0126: Read Receiver Tuning Parameters

    PMA attributes. The analog parameters can be read or changed when the transceiver is running. Related Information • Configuring a PMA Parameter Tunable by the Adaptive Engine on page 155 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 183 After updating the analog parameter value, the parameters listed below need to be loaded into the receiver to become effective. Use attribute code 0x00EC and the following table to load the parameters into the transceiver. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 184: Pma Registers 0X200 To 0X203 Usage

    Use registers 0x200 to 0x203 as an alternative method to set certain PMA attributes or to perform a PMA analog reset. For details, refer to Loading a PMA Configuration. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 185 Adaptation and Put PMA in Mission Mode, and Read the Physical Channel Number for how to set registers 0x200 to 0x203. Related Information • Loading a PMA Configuration on page 163 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 186: Pma Analog Reset

    {0x201[0],0x200[7:5]}: 4’h2 to set the PRBS generator and checker in PRBS11 mode after initial adaption is complete. • {0x201[0],0x200[7:5]}: 4’h3 to set the PRBS generator and checker in PRBS13 mode after initial adaption is complete. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 187: Read The Physical Channel Number

    PMA attribute code 0x0005 or 0x0006. Table 62. Data Rate Ratios for PMA Attribute 0x0005 or 0x0006 Supported Above 15 Ratio 1/2 Rate 1/4 Rate 1/8 Rate Gbaud per Second continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 188 9. Register Map UG-20056 | 2019.02.04 Supported Above 15 Ratio 1/2 Rate 1/4 Rate 1/8 Rate Gbaud per Second continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 189 9. Register Map UG-20056 | 2019.02.04 Supported Above 15 Ratio 1/2 Rate 1/4 Rate 1/8 Rate Gbaud per Second continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 190: Rs-Fec Registers

    Defines the configuration fields for TX Deskew 0x0000 0000 0x30 rsfec_core_cfg RS-FEC core configuration 0x0000 0000 0x40 rsfec_lane_cfg_0 RS-FEC per lane configuration 0x0000 0000 0x44 rsfec_lane_cfg_1 0x48 rsfec_lane_cfg_2 0x4C rsfec_lane_cfg_3 continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 191 RX lane interrupt 0x1A0 rsfec_ln_mapping_rx_0 RS-FEC FEC lane mapping 0x0000 0000 0x1A4 rsfec_ln_mapping_rx_1 0x1A8 rsfec_ln_mapping_rx_2 0x1AC rsfec_ln_mapping_rx_3 0x1B0 rsfec_ln_skew_rx_0 RS-FEC lane skew 0x0000 0000 0x1B4 rsfec_ln_skew_rx_1 continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 192 0x23C rsfec_uncorr_cw_cnt_3_hi 0x240 rsfec_corr_syms_cnt_0_lo RS-FEC number of 10b symbols corrected for the lane (low word: 0x0000 0000 bits 31 to 0) 0x248 rsfec_corr_syms_cnt_1_lo 0x250 rsfec_corr_syms_cnt_2_lo 0x258 rsfec_corr_syms_cnt_3_lo continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 193: Rsfec_Top_Clk_Cfg

    0x294 rsfec_corr_1s_cnt_2_hi 0x29C rsfec_corr_1s_cnt_3_hi All statistic registers are 64 bits, and you must do two 32-bit reads. Intel recommends that you enable the in offset address 0x108 explained in shadow_req[3:0] rsfec_debug_cfg before reading the statistics register and disable after reading it.

  • Page 194: Rsfec_Top_Tx_Cfg

    3'b111 : Debug Mode - Select Loopback from output of RS-FEC RX core_tx_in_sel1 RS-FEC TX Select For Lane 1 Indicates which data to select for rsfec core TX input continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 195: Rsfec_Top_Rx_Cfg

    2'b00 : Bypass RS-FEC RX paths - data from XCVRIF fec / pcs path (normal bypass) 2'b01 : Select output of RS-FEC RX. 2'b10 : Bypass RS-FEC RX paths - data from XCVRIF fec path for both ehip and elane continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 196: Tx_Aib_Dsk_Conf

    1:TX AIB deskew circuit in reset tx_deskew_chan_sel Specifies which channels to include in the deskew procedure 1= include 9.5.5. rsfec_core_cfg Description Address Addressing Mode RS-FEC core configuration 0x30 32-bits ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 197: Rsfec_Lane_Cfg

    (i.e. 32GFC), otherwise it must be set to 0. Set to enable Fibre Channel mode. 9.5.7. tx_aib_dsk_status Description Address Addressing Mode Status fields for TX Deskew 0x104 32-bits ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 198: Rsfec_Debug_Cfg

    1: Clear the collection and shadow counters so that the next shadow request or snapshot will start from 0. If the counters are not cleared, they will continue counting and rollover. shadow_req ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 199: Rsfec_Lane_Tx_Stat

    With RS544 .pace_inv is set when the layer above presents TX data in more than 33 consecutive cycles. resync PCS Tx alignment/codeword marker resync. Not valid when RSFEC_LANE_CFG1.eng_cust_am_en = 1. blk_inv PCS Tx 66b invalid block type. continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 200: Rsfec_Lane_Tx_Inten

    Not valid when transcoding is bypassed. 9.5.12. rsfec_lane_rx_stat Register Name Description Address Addressing Mode rsfec_lane_rx_stat_0 RS-FEC per lane RX status 0x150 32-bits rsfec_lane_rx_stat_1 0x154 rsfec_lane_rx_stat_2 0x158 rsfec_lane_rx_stat_3 0x15C ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 201: Rsfec_Lane_Rx_Hold

    Set when a FEC code word could not be corrected due to too many errors. corr_cw Set when a FEC code word had one or more errors that were corrected. hi_ser High symbol error rate. continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 202: Rsfec_Lane_Rx_Inten

    PCS layer for a period of 60ms to 75ms. am_5bad RX was locked (and aligned if RSFEC_CORE_CFG.frac = none) but 5 consecutive alignment/codeword markers were not valid. continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 203: Rsfec_Lanes_Rx_Stat

    All RX lanes locked but the alignment markers were not unique or the skew was too large. This is an event signal, so use .not_align above instead to determine the alignment state. Restarts the synchronization. continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 204: Rsfec_Lanes_Rx_Inten

    The reset values in this table represents register values after a reset has completed. Name Description SW Access Reset HW Access Protection fec_lane FEC lane# received on each physical lane. Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC). ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 205: Rsfec_Ln_Skew_Rx

    Reset HW Access Protection 15:8 SRAM ECC uncorrectable error detected. 0x00 Same bit ordering as for .sbe above. WO1S SRAM ECC correctable (single bit) error detected. 0x00 continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 206: Rsfec_Err_Inj_Tx

    The reset values in this table represents register values after a reset has completed. Name Description SW Access Reset HW Access Protection 15:8 inj1s Same for bits changed from 0 to 1 on each physical lane. 0x00 continued... ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 207: Rsfec_Corr_Cw_Cnt (Low)

    The reset values in this table represents register values after a reset has completed. Name Description SW Access Reset HW Access Protection 31:0 stat Statistics value. 0x0000 0000 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 208: Rsfec_Uncorr_Cw_Cnt (Low)

    The reset values in this table represents register values after a reset has completed. Name Description SW Access Reset HW Access Protection 31:0 stat Statistics value. 0x0000 0000 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 209: Rsfec_Corr_Syms_Cnt (High)

    The reset values in this table represents register values after a reset has completed. Name Description SW Access Reset HW Access Protection 31:0 stat Statistics value. 0x0000 0000 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 210: Rsfec_Corr_0S_Cnt (High)

    The reset values in this table represents register values after a reset has completed. Name Description SW Access Reset HW Access Protection 31:0 stat Statistics value. 0x0000 0000 ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 211: Register Map Revision History

    Added bit offsets [3:2] and [4] to address 0x9 in the "PMA Register Map" table. • Removed addresses 0x50040 and 0x50041 in the "PMA Capability Register Map" table. • Added address 0x8B to the "PMA Register Map" table. 2018.01.31 Initial release. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 212: E-Tile Channel Placement Tool

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 213 Renamed the "Channel Use Model" appendix to "E-Tile Channel Placement Tool." • Removed PMA-Direct Single Channel Mode, PMA-Direct Dual Channel Mode, and Precision Time Protocol (PTP) Placement. • Added a description, screenshot and link to the "E-Tile Channel Placement Tool" and Intel Stratix 10 PCG. 2018.01.31 Initial release. ®...

  • Page 214: Pma Direct Pam4 30 Gbps To 57.8 Gbps Implementation

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 215 B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation UG-20056 | 2019.02.04 Figure 102. E-Tile Channel Placement Tool Two adjacent core interfaces for a single PAM4 FEC mode 12 even channels channel PMA direct is off ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 216 PMA CH3 (10G /25G) MAC + PCS PMA CH2 (528, 514) PMA CH1 or (544, 514) (Aggregate: EHIP_CORE PMA CH0 100G) (100G MAC (Fractured: + PCS) 25G) EHIP_TOP ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...
  • Page 217 PMA CH15 (10G /25G) MAC + PCS PMA CH14 (528, 514) PMA CH13 or (544, 514) (Aggregate: EHIP_CORE PMA CH12 100G) (100G MAC (Fractured: + PCS) 25G) EHIP_TOP ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 218: Starting A New Intel Quartus Prime Pro Edition Design

    Intel Stratix 10 E-Tile Channel Placement Tool B.2. Starting a New Intel Quartus Prime Pro Edition Design This design example uses Intel Quartus Prime Pro Edition software version 18.0. 1. Click File > New Project Wizard. 2. Select a project folder, then keep clicking Next until you see Family, Device &...

  • Page 219: Selecting The Configuration Clock Source

    B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation UG-20056 | 2019.02.04 Figure 106. Family, Device & Board Settings Refer to the Intel Stratix 10 Device Datasheet for E-Tile specifications. Related Information Intel Stratix 10 Device Datasheet B.3. Selecting the Configuration Clock Source Use this procedure to set the clock for the transceiver reset sequence (TRS) and local TRS (LTRS) blocks.

  • Page 220: Instantiating The Transceiver Native Phy Ip

    OSC_CLK_1 pin, or 25 MHz OSC_CLK_1 pin in the Configuration clock source field depending on your clock frequency's availability. Figure 108. Configuration Clock Source Selection B.4. Instantiating the Transceiver Native PHY IP This procedure describes how to instantiate your Intel Stratix 10 E-Tile Transceiver Native PHY IP core. ® ®...
  • Page 221 B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation UG-20056 | 2019.02.04 1. Locate the Stratix 10 E-Tile Transceiver Native PHY IP core in the IP Catalog. Figure 109. IP Catalog The Native PHY IP Parameter Editor allows you to set many configurations, such •...
  • Page 222 30 Gbps, two adjacent channels are combined to provide a single PAM4 channel. So, total 24/2 = 12 PAM4 channels. Note: You must set the TX PMA tab as well. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 223: Instantiating The In-System Sources And Probes Intel Fpga Ip

    64 TX/RX PMA interface width. B.5. Instantiating the In-system Sources and Probes Intel FPGA IP This procedure describes how to instantiate the In-System Sources and Probes Intel FPGA IP core. This IP is used as a reset signal in Making the Top Level Connection.

  • Page 224: Making The Top Level Connection

    2. Double-click In-System Sources & Probes Intel FPGA IP. 3. Name the IP, 4. Configure the IP with these settings. Figure 113. In-System Source & Probes Intel FPGA IP Configuration Related Information Making the Top Level Connection on page 224 B.6.
  • Page 225 .tx_parallel_data( {12{48'b0,32'h0f0f0f0f, 48'b0, 32'h0f0f0f0f}} ), // tx_parallel_data.tx_parallel_data .tx_pma_ready( tx_pma_ready.tx_pma_ready .tx_ready( tx_ready.tx_ready .tx_serial_data( tx_serial_data ), tx_serial_data.tx_serial_data .tx_serial_data_n( tx_serial_data_n ) tx_serial_data_n.tx_serial_data_n src src ( .probe( probes.probe .source( source ) // sources.source ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

  • Page 226: Assigning Pins

    2. Download the settings to the board by clicking the Programmer tool. Figure 114. Programmer Tool 3. Click Auto Detect to detect devices, then locate the Intel Stratix 10 device. 4. Next to the Intel Stratix 10 device, Click Change file to locate and add the .sof file. ®...

  • Page 227: Debug Tools

    The Signal Tap Logic Analyzer helps you perform transceiver debug operations. You can also use Transceiver Toolkit to perform transceiver debug operations. Refer to the Intel Quartus Prime Pro Edition User Guide: Debug Tools for more information about the Transceiver Toolkit.

  • Page 228: Pma Direct Pam4 30 Gbps To 57.8 Gbps Implementation Revision History

    Updated GUI figures in Instantiating the Transceiver Native PHY IP. 2018.07.18 Made the following changes: • Added further description and a link to the Transceiver Toolkit documentation in the "Debug Tools" section. 2018.05.15 Initial release. ® ® Intel Stratix 10 E-Tile Transceiver PHY User Guide Send Feedback...

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