Intel Cyclone 10 GX User Manual page 154

Figure 74. Signals and Ports of Native PHY IP for CPRI
rx_is_lockedtodata
rx_is_lockedtoref
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller.
You can use your own reset controller or use the Native PHY Reset Controller IP.
7. Connect the Native PHY IP to the PLL IP core and the reset controller. Use the
information in the following figure to connect the ports.
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Intel Cyclone 10 GX Transceiver PHY User Guide
154
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
tx_cal_busy
NIOS
rx_cal_busy Hard Calibration IP
TX PMA
tx_serial_data Serializer
Local Clock
tx_serial_clk0
Generation
(from TX PLL)
Block
RX PMA
Deserializer
rx_serial_data
rx_cdr_refclk0
CDR
Cyclone 10 Transceiver Native PHY
Reconfiguration
Registers
TX Standard PCS
tx_parallel_data
10/20
unused_tx_parallel_data[118:0]
RX Standard PCS
rx_parallel_data
10/20
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_std_wa_patternalign
unused_rx_parallel_data[118:0]
UG-20070 | 2018.09.24
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digital_reset
tx_datak tx_datak[1:0]
tx_parallel_data[15:0]
tx_coreclkin tx_coreclkin
tx_clkout tx_clkout
tx_analog_reset
rx_analog_reset
rx_digital_reset
rx_datak rx_datak[1:0]
rx_parallel_data[15:0]
rx_clkout rx_clkout
rx_coreclkin rx_coreclkin
rx_errdetect rx_errdetect[1:0]
rx_disperr rx_disperr[1:0]
rx_runningdisp[1:0]
rx_patterndetect[1:0]
rx_syncstatus[1:0]
rx_std_wa_patternalign
unused_rx_parallel_data[118:0]
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