Intel Cyclone 10 GX User Manual page 167

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 83. Transceiver Channel Datapath and Clocking for the Basic and Basic with Rate
Match Configurations
The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width
is 10 bits.
625 MHz (2)
Notes:
1. The parallel clock (tx_clkout or rx_clkout) is calculated as data rate/PCS-PMA interface width =1250/10 = 125 MHz.
When the Byte Serializer is set to Serialize x2 mode, tx_clkout and rx_clkout become 1250/20 = 62.5 MHz.
2. The serial clock is calculated as data rate/2. The PMA runs on a dual data rate clock.
3. This block is only enabled when using the Basic with Rate Match transceiver configuration rule.
In low latency modes, the transmitter and receiver FIFOs are always enabled.
Depending on the targeted data rate, you can optionally bypass the byte serializer and
deserializer blocks.
Send Feedback
Transmitter PMA
10
tx_clkout
125 MHz (1)
tx_pma_div_clkout
Receiver PMA
10
Parallel Clock
(Recovered) rx_clkout
125 MHz (1)
tx_clkout
Parallel Clock
(From Clock
Divider)
Parallel Clock
Serial Clock
Parallel and Serial Clock
PRBS
Generator
/2
/2
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clock
®
Intel Cyclone
Transmitter Standard PCS
FPGA
Fabric
16
tx_coreclkin
62.5 MHz (1)
tx_clkout
Receiver Standard PCS
16
rx_coreclkin
62.5 MHz (1)
rx_clkout or
tx_clkout
ATX PLL
CMU PLL
fPLL
Serial Clock
®
10 GX Transceiver PHY User Guide
167