Intel Cyclone 10 GX User Manual page 130

Figure 65. Use ATX PLL or fPLL for Gen1/Gen2 x4 Mode
fPLL1
ATX PLL1
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x4 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines.
4. Gen1/Gen2 x4 modes use either ATX PLL or fPLL only.
5. Connect pll_pcie_clk from either ATX PLL or fPLL to the pipe_hclk_in port on Native PHY.
6. In this case the Master PCS channel is logical channel 3 (physical channel 4).
Related Information
• Using PLLs and Clock Networks
For more information about implementing clock configurations and configuring
PLLs.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
130
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
XN
Network
6
Connections Done
via X1 Network
Master
CGB1
Master
CGB0
on page 231
X6
Network
6 6
6
6
6
UG-20070 | 2018.09.24
Ch 5
CGB
CDR
Ch 4
CGB
CDR
Ch 3
CGB
CDR
Ch 2
CGB
CDR
Ch 1
CGB
CDR
Ch 0
CGB
CDR
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