Intel Cyclone 10 GX User Manual page 336

When performing a reference clock switch, you must specify the lookup register
address and respective bits of the replacement clock. After determining the ATX PLL,
follow this procedure to switch to the selected reference clock:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the lookup register address and save the required 8-bit pattern. For
example, switching to logical
0x115
3. Perform a read-modify-write to bits
obtained from the lookup register.
4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
Steps to Perform Dynamic Reconfiguration
6.11.2.2. fPLL Reference Clock Switching
You can use the reconfiguration interface on the fPLL instance to specify which
reference clock source drives the fPLL. The fPLL supports clocking by up to five
different reference clock sources. The flow to select between the different reference
clock sources is independent of the number of transmitter PLLs specified in the
reconfiguration interface.
Before initiating a reference clock switch, ensure that your fPLL instance defines more
than one reference clock source. Specify the Number of PLL reference clocks
parameter on the PLL tab during fPLL parameterization.
The following table shows the addresses and bits for switching between fPLL reference
clock inputs. The number of exposed
number of reference clocks you specify. Use the fPLL reconfiguration interface for this
operation.
Table 181. Register Map for Switching fPLL Reference Clock Inputs
Transceiver fPLL Port
pll_refclk0
pll_refclk1
pll_refclk2
pll_refclk3
pll_refclk4
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
336
refclk2
.
Description
Represents logical
refclk0
register stores the mapping from logical
x117[4:0]
to the physical refclk for MUX_0.
refclk0
Represents logical
refclk1
register stores the mapping from logical
x118[4:0]
to the physical refclk for MUX_0.
refclk1
Represents logical
refclk2
register stores the mapping from logical
x119[4:0]
to the physical refclk for MUX_0.
refclk2
Represents logical
refclk3
register stores the mapping from logical
x11A[4:0]
to the physical refclk for MUX_0.
refclk3
Represents logical
refclk4
register stores the mapping from logical
x11B[4:0]
to the physical refclk for MUX_0.
refclk4
6. Reconfiguration Interface and Dynamic Reconfiguration
requires use of bits
at address
[7:0]
on page 328
ports varies according to the
pll_refclk
0x117 (Lookup Register)
for . Lookup
MUX_0
0x118 (Lookup Register)
for . Lookup
MUX_0
0x119 (Lookup Register)
for . Lookup
MUX_0
0x11A (Lookup Register)
for . Lookup
MUX_0
0x11B (Lookup Register)
for . Lookup
MUX_0
UG-20070 | 2018.09.24
at address
[7:0]
using the 8-bit value
0x112
Address Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
continued...
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