Dedicated Reference Clock Pins; Receiver Input Pins - Intel Cyclone 10 GX User Manual

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
Related Information
Calibration
For more information about the calibration process

3.2.1. Dedicated Reference Clock Pins

To minimize the jitter, the advanced transmit (ATX) PLL and the fractional PLL (fPLL)
can source the input reference clock directly from the reference clock buffer without
passing through the reference clock network. The input reference clock is also fed into
the reference clock network.
Figure 123. Dedicated Reference Clock Pins
There are two dedicated reference clock (
pin feeds the bottom ATX PLL and fPLL. The top
reference clock pins including the 4 channels bank can also drive the reference clock network.
fPLL1
ATX PLL1
fPLL0
ATX PLL0

3.2.2. Receiver Input Pins

Receiver input pins can be used as an input reference clock source to transceiver PLLs.
However, they cannot be used to drive core fabric.
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refclk
CH5
CDR PLL
CH4
CMU PLL
CH3
CDR PLL
CH2
CDR PLL
CH1
CMU PLL
CH0
CDR PLL
) pins available in each transceiver bank. The bottom
pin feeds the top ATX PLL and fPLL. The dedicated
refclk
Reference Clock
Network
From PLL
Cascading Clock
Network
Reference Clock
Network
From PLL Feedback
and Cascading Clock
Network
From PLL
Cascading Clock
Network
Reference Clock
Network
From PLL Feedback
and Cascading Clock
Network
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
refclk
Refclk
Input Reference Clock to the PLLs
Can Come from Either the Reference
Clock Network or the PLL Feedback
and Cascading Clock Network
Refclk
ATX and fPLL Can Receive the
Input Reference Clock from a
Dedicated refclk Pin
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