How To Implement Pci Express (Pipe) In Cyclone 10 Gx Transceivers; Native Phy Ip Parameter Settings For Pipe - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
• PIPE Design Example
For more information about the PLL configuration for PCIe.
• Transmit PLL recommendation based on Data rates
For more information about ATX PLL placement restrictions
2.7.4. How to Implement PCI Express (PIPE) in Cyclone 10 GX
Transceivers
You must be familiar with the Standard PCS architecture, PLL architecture, and the
reset controller before implementing the PCI Express protocol.
1. Go to the IP Catalog and select the Cyclone 10 GX Transceiver Native PHY IP
Core. Refer to
2. Select Gen1/Gen2 PIPE from the Cyclone 10 GX Transceiver configuration
rules list, located under Datapath Options.
3. Use the parameter values in the tables in
PCI Express Transceiver Configurations Rules
can use Cyclone 10 GX Transceiver Native PHY Presets . You can then modify
the settings to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7. Connect the Native PHY IP to the PLL IP core and the reset controller. Use the
information in
Configuration Rules
8. Simulate your design to verify its functionality.

2.7.5. Native PHY IP Parameter Settings for PIPE

Table 120. Parameters for Cyclone 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes
This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter
Message level for rule violations
Common PMA Options
VCCR_GXB and VCCT_GXB supply voltage
for the Transceiver
Transceiver link type
Datapath Options
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Send Feedback
Select and Instantiate the PHY IP Core
Transceiver Native PHY IP Ports for PCI Express Transceiver
to connect the ports.
Gen1 PIPE
Error
Gen1: 0_9V
Gen1: sr
Gen1 PIPE
Basic
TX / RX Duplex
Gen1 x1: 1 channel
on page 200
on page 17 for more details.
Transceiver Native PHY IP Parameters for
as a starting point. Alternatively, you
Gen2 PIPE
Error
Gen2: 0_9V
Gen2: sr
Gen2 PIPE
Basic
TX / RX Duplex
Gen2 x1: 1 channel
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Intel Cyclone 10 GX Transceiver PHY User Guide
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