Connect The Phy Ip To The Pll Ip Core And Reset Controller; Connect Datapath; Make Analog Parameter Settings; Compile The Design - Intel Cyclone 10 GX User Manual

2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller

Connect the PHY IP, PLL IP core, and the reset controller. Write the top level module to
connect all the IP blocks.
All of the I/O ports for each IP, can be seen in the <phy instance name>.v file or <phy
instance name>.vhd, and in the <phy_instance_name>_bb.v file.
For more information about description of the ports, refer to the ports tables in the
PLLs, Using the Transceiver Native PHY IP Core, and Resetting Transceiver Channels
chapters.
Related Information
• Resetting Transceiver Channels
• Using the Cyclone 10 GX Transceiver Native PHY IP Core
• PLLs and Clock Networks

2.2.10. Connect Datapath

Connect the transceiver PHY layer design to the Media Access Controller (MAC) IP core
or to a data generator / analyzer or a frame generator / analyzer.

2.2.11. Make Analog Parameter Settings

Make analog parameter settings to I/O pins using the Assignment Editor or updating
the Quartus Prime Settings File.
After verifying your design functionality, make pin assignments and PMA analog
parameter settings for the transceiver pins.
1. Assign FPGA pins to all the transceiver and reference clock I/O pins.
2. Set the analog parameters to the transmitter, receiver, and reference clock pins
using the Assignment Editor.
All of the pin assignments and analog parameters set using the Pin Planner and
the Assignment Editor are saved in the <top_level_project_name>.qsf file. You
can also directly modify the Quartus Settings File (.qsf) to set PMA analog
parameters.

2.2.12. Compile the Design

To compile the transceiver design, add the <phy_instancename>.qip files for all the IP
blocks generated using the IP Catalog to the Quartus Prime project library. You can
alternatively add the .qsys and .qip variants of the IP cores.
Note: If you add both the .qsys and the .qip file into the Quartus Prime project, the
software generates an error.

2.2.13. Verify Design Functionality

Simulate your design to verify the functionality of your design. For more details, refer
to Simulating the Native Transceiver PHY IP Core section.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
22
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
on page 243
on page 198
UG-20070 | 2018.09.24
on page 26
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