Intel Cyclone 10 GX User Manual page 213

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
For bonded configuration mode, the low speed parallel clock output of the master CGB
is used and the local CGB within each channel is bypassed. For non-bonded
configurations, the master CGB also provides a high speed serial clock output to each
channel without bypassing the local CGB within each channel.
The x6 clock lines also drive the xN clock lines which route the clocks to the
neighboring transceiver banks.
Figure 125. x6 Clock Lines
Send Feedback
x6
Top
Master
CGB
Master
CGB
x6
Network
x6
Bottom
CGB
CGB
CGB
CGB
CGB
CGB
®
Intel Cyclone
Ch 5
CDR
Ch 4
CMU or CDR
Ch 3
CDR
Ch 2
CDR
Ch 1
CMU or CDR
Ch 0
CDR
®
10 GX Transceiver PHY User Guide
213