Intel Cyclone 10 GX User Manual page 251

4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Figure 151. Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock
Mode
Control Signals
rx_set_locktoref
rx_set_locktodata
rx_digitalreset
rx_analogreset
Status Signals
rx_is_lockedtoref
rx_is_lockedtodata
4.3.1.1.3. Resetting the Transceiver Channel During Device Operation
The numbers in this list correspond to the numbers in the following figure.
1. Assert
rx_analogreset
tx_cal_busy
2. Deassert
minimum duration of 70 μs.
3. The
pll_locked
minimum 70 μs after deasserting
signal.
4. Deassert
tx_digitalreset
(minimum of 70 μs) duration after
5. Deassert
6. Ensure
deasserting
Send Feedback
2
1
2
1
1
2
1
rx_ready 3
1
rx_cal_busy
,
tx_analogreset pll_powerdown
, and
rx_digitalreset
, and
rx_cal_busy
and
pll_powerdown
signal goes high after the TX PLL acquires lock. Wait for a
tx_digitalreset
signal must stay asserted for a minimum
rx_analogreset
rx_is_lockedtodata
rx_digitalreset
t
LTD_Manual
4
,
tx_digitalreset
. Ensure that
are low.
at the same time, after a
tx_analogreset
tx_analogreset
after goes high. The
pll_locked
tx_analogreset
after deasserting
tx_analogreset
is asserted for t (minimum of 4 μs) before
LTD
.
®
Intel Cyclone
4
5
t
LTD_Manual
4
6
,
,
pll_cal_busy
to monitor the
pll_locked
t
tx_digitalreset
is deasserted.
.
®
10 GX Transceiver PHY User Guide
251