Intel Cyclone 10 GX User Manual page 9

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1. Intel Cyclone 10 GX Transceiver PHY Overview
UG-20070 | 2018.09.24
Figure 2. Intel Cyclone 10 GX Devices with 12 Transceiver Channels and One PCIe Hard
IP Block
CH5
CH4
CH3
CH2
CH1
CH0
Legend:
PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Cyclone 10 GX device with 12 transceiver channels and one PCIe Hard IP block.
Figure 3. Intel Cyclone 10 GX Devices with 10 Transceiver Channels and One PCIe Hard
IP Block
CH5
CH4
CH3
CH2
CH1
CH0
Legend:
PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Cyclone 10 GX device with 10 transceiver channels and one PCIe Hard IP block.
Figure 4. Intel Cyclone 10 GX Devices with 6 Transceiver Channels and One PCIe Hard
IP Block
CH5
CH4
CH3
CH2
CH1
CH0
Note:
(1) Only CH5 and CH4 support PCIe Hard IP block with CvP capabilities.
Legend:
PCIe Gen1 - Gen2 Hard IP block with Configuration via Protocol (CvP) capabilities.
Cyclone 10 GX device with six transceiver channels and one PCIe Hard IP block.
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GXBL1D
Transceiver
Bank
GXBL1C
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
GXBL1C GXBL1C
Transceiver Transceiver
PCIe
Bank Bank
Gen1 - Gen2
Hard IP
(with CvP)
Transceiver Transceiver
Bank Bank
Transceiver Transceiver
PCIe
Bank Bank
Gen1 - Gen2
Hard IP
(with CvP)
Transceiver Transceiver
Bank Bank
PCIe Gen1 - Gen2 Hard IP (with CvP) (1)
Transceiver Transceiver
Bank Bank
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Intel Cyclone 10 GX Transceiver PHY User Guide
9