Intel Cyclone 10 GX User Manual page 95

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 42. Connection Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design
Note:
1. The pll_cal_busy signal is not available when using the CMU PLL.
2. The pll_powerdown signal is not available separately for user control when using the fPLL.
8. Simulate your design to verify its functionality.
2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
This section contains the recommended parameter values for this protocol. Refer to
Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of
parameter values.
Table 85. General and Datapath Options
The first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general
and datapath options to customize the transceiver.
Message level for rule violations
Transceiver configuration rules
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Send Feedback
reset
pll_ref_clk
pll_locked
PLL
pll_powerdown (2)
rx_ready
tx_ready
clk
reset
pll_cal_busy (1)
reset
tx_serial_clk
The reset controller handles PLL reset for the fPLL.
Parameter
tx_parallel_data
Pattern
tx_datak
Generator
tx_clkout
tx_digitalreset
tx_analogreset
Reset
rx_digitalreset
Controller
rx_analogreset
rx_is_lockedtodata
rx_cal_busy
rx_cdr_refclk
tx_cal_busy
rx_parallel_data
rx_datak
Pattern
Checker
rx_clkout
GbE 1588 (for GbE with IEEE 1588v2)
®
Intel Cyclone
tx_serial_data
rx_serial_data
Cyclone 10
Transceiver
Native
PHY
Value
error
warning
GbE (for GbE)
TX/RX Duplex
TX Simplex
RX Simplex
1 to 12
1250 Mbps
On/Off
On/Off
®
10 GX Transceiver PHY User Guide
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