Intel Cyclone 10 GX User Manual page 33

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Parameter
Selected CDR reference
clock
Selected CDR reference
clock frequency
PPM detector threshold
Table 10. Equalization
Parameters
CTLE adaptation mode
Table 11. RX PMA Optional Ports
Parameters
Enable
rx_analog_reset_ack
port
Enable rx_pma_clkout
port
Enable
rx_pma_div_clkout
port
rx_pma_div_clkout
division factor
Enable
rx_pma_iqtxrx_clkout
port
(12)
This clock should not be used to clock the FPGA - transceiver interface. This clock may be used
as a reference clock to an external clock cleaner.
(13)
The default value is Disabled.
Send Feedback
Value
Use this feature when you want to dynamically re-configure CDR
reference clock source.
0 to <number of Specifies the initial CDR reference clock. This parameter
CDR reference determines the available CDR references used.
clocks> -1
The default value is 0.
< data rate Specifies the CDR reference clock frequency. This value depends
dependent > on the data rate specified.
100 Specifies the PPM threshold for the CDR. If the PPM between the
incoming serial data and the CDR reference clock, exceeds this
300
threshold value, the CDR loses lock.
500
The default value is 1000.
1000
Value
Manual Specifies the Continuous Time Linear Equalization (CTLE)
operation mode.
For manual mode, set the CTLE options through the Assignment
Editor, or modify the Quartus Settings File (.qsf), or write to the
reconfiguration registers using the Avalon Memory-Mapped
(Avalon-MM) interface.
Refer to the Continuous Time Linear Equalization (CTLE) section
for more details about CTLE architecture. Refer to the How to
Enable CTLE section for more details on supported adaptation
modes.
Value
On/Off
Enables the optional
should not be used for register mode data transfers.
On/Off
Enables the optional
the recovered parallel clock from the RX clock data recovery
(CDR).
On/Off
Enables the optional
deserializer generates this clock. Use this to drive core logic, to
drive the RX PCS-to-FPGA fabric interface, or both.
If you select a rx_pma_div_clkout division factor of 1 or 2, this
clock output is derived from the PMA parallel clock. If you select a
rx_pma_div_clkout division factor of 33, 40, or 66, this clock is
derived from the PMA serial clock. This clock is commonly used
when the interface to the RX FIFO runs at a different rate than the
PMA parallel clock frequency, such as 66:40 applications.
Disabled, 1, 2, 33, 40,
Selects the division factor for the
66
clock when enabled.
On/Off Enables the optional
clock can be used to cascade the RX PMA output clock to the input
of a PLL.
Description
Description
Description
rx_analog_reset_ack
rx_pma_clkout
(12)
rx_pma_div_clkout
rx_pma_div_clkout
(13)
rx_pma_iqtxrx_clkout
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
output. This port
output clock. This port is
output clock. The
output
output clock. This
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