Intel Cyclone 10 GX User Manual page 127

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 61. Rate Match FIFO Empty
The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to become
empty and drives
below shows rate match FIFO empty condition in PIPE mode. The rate match FIFO becomes empty after
reading out data byte D3.
tx_parallel_data
rx_parallel_data
pipe_rx_status[2:0]
PIPE 0 ppm
The PIPE mode also has a "0 ppm" configuration option that can be used in
synchronous systems. The Rate Match FIFO Block is not expected to do any clock
compensation in this configuration, but latency will be minimized.
2.7.2.1.8. PCIe Reverse Parallel Loopback
PCIe reverse parallel loopback is only available in a PCIe functional configuration for
Gen1 and Gen2 data rates. The received serial data passes through the receiver CDR,
deserializer, word aligner, and rate matching FIFO buffer. The data is then looped back
to the transmitter serializer and transmitted out through the transmitter buffer. The
received data is also available to the FPGA fabric through the
port. This loopback mode is based on PCIe specification 2.0. Cyclone 10 GX devices
provide an input signal
mode.
Note: This is the only loopback option supported in PIPE configurations.
Figure 62. PCIe Reverse Parallel Loopback Mode Datapath
Transmitter PMA
Receiver PMA
Related Information
• Cyclone 10 GX Standard PCS Architecture
• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 2.0
Send Feedback
= 3'b110 synchronous to the inserted /K30.7/ (9'h1FE). The figure
pipe_rx_status[2:0]
D1 D2
D1 D2
xxx xxx
pipe_tx_detectrx_loopback[0:0]
PRBS
Reverse Parallel Generator
Loopback Path
PRBS
Verifier
D3 D4 D5
D3 /K.30.7/ D4
xxx 3'b110 xxx
rx_parallel_data
to enable this loopback
Transmitter Standard PCS
Receiver Standard PCS
on page 299
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
D6
D5
xxx
FPGA
Fabric
127