Metaframe Format And Framing Layer Control Word - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 16. Transceiver Channel Datapath and Clocking for Interlaken
This figure assumes the serial data rate is 12.5 Gbps and the PMA width is 40 bits.
Transmitter PMA Transmitter Enhanced PCS
40
Receiver PMA Receiver Enhanced PCS
40
PRBS
Verifier
Div 40
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Related Information
• Interlaken Protocol Definition v1.2
• Interlaken Look-Aside Protocol Definition, v1.1

2.5.1. Metaframe Format and Framing Layer Control Word

The Enhanced PCS supports programmable metaframe lengths from 5 to 8192 words.
However, for stability and performance, Intel recommends you set the frame length to
no less than 128 words. In simulation, use a smaller metaframe length to reduce
simulation times. The payload of a metaframe could be pure data payload and a
Burst/Idle control word from the MAC layer.
Send Feedback
PRBS
Generator
Clock Generation Block (CGB)
PRP
Generator
Parallel Clock (312.5 MHz)
PRP
Verifier
Parallel Clock (312.5 MHz)
10GBASE-R
BER Checker
Clock Divider
Parallel and Serial Clocks
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
64 bits
data +
3 bits
control
186.57 MHz
to 312.5MHz
tx_pma_div_clkout
rx_pma_div_clkout
64 bits
data +
3 bits
control
186.57 MHz
to 312.5MHz
(6.25 GHz) =
Data rate/2
ATX PLL
fPLL
CMU PLL
Serial Clock
Input Reference Clock
71
FPGA
Fabric
tx_clkout
rx_clkout