Intel Cyclone 10 GX User Manual page 129

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 64. Use ATX PLL for Gen1/Gen2 x1 Mode
Path for Clocking in
Gen1/Gen2 x1 Mode
Send Feedback
fPLL1
ATX PLL1
Master 4
CGB1
fPLL0
4
Master
CGB0
ATX PLL0
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x1 mode.
2. Gen1/Gen2 x1 mode uses the ATX PLL or fPLL.
3. Gen1/Gen2 x1 can use any channel from the given bank for which the ATX PLL or fPLL is enabled.
4. Connect pll_pcie_clk from either ATX PLL or fPLL to the pipe_hclk_in port on Native PHY.
X1 Network
6
CGB
6
CGB
6
CGB
6
CGB
6
CGB
6
CGB
®
Intel Cyclone
Ch 5
CDR
Ch 4
CDR
Ch 3
CDR
Ch 2
CDR
Ch 1
Path for Clocking in
Gen1/Gen2 x1 Mode
CDR
Ch 0
CDR
®
10 GX Transceiver PHY User Guide
129