Intel Cyclone 10 GX User Manual page 215

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
Figure 126. xN Clock Network
Related Information
• Implementing x6/xN Bonding Mode
• x6/xN Bonding
• Cyclone 10 GX Data Sheet.
Send Feedback
xN Up xN Down
Top
Master
CGB1
Master
CGB0
xN Up xN Down
on page 222
x6 x6
Bottom
CGB
CGB
CGB
CGB
CGB
CGB
on page 236
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
Ch 5
CDR
Ch 4
CMU or CDR
Ch 3
CDR
Ch 2
CDR
Ch 1
CMU or CDR
Ch 0
CDR
215