Unused/Idle Clock Line Requirements - Intel Cyclone 10 GX User Manual

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
Figure 131. Receiver Standard PCS and PMA Clocking
Receiver PMA
All configurations that use the standard PCS channel must have a 0 ppm phase
difference between the receiver datapath interface clock and the read side clock of the
RX phase compensation FIFO.
Figure 132. Receiver Enhanced PCS and PMA Clocking
Receiver PMA
The receiver PCS forwards the following clocks to the FPGA fabric:
Parallel Clock
•
rx_clkout
Parallel and Serial Clock
•
tx_clkout
You can clock the receiver datapath interface using one of the following methods:
• Quartus Prime selected receiver datapath interface clock
• User-selected receiver datapath interface clock
Related Information
Unused or Idle Clock Line Requirements
For more information about unused or idle transceiver clock lines in design.

3.8. Unused/Idle Clock Line Requirements

Unused or idle transceiver clock lines can degrade if the devices are powered up to
normal operating conditions and the devices are not configured. This issue also affects
designs that will configure transceiver channels to use the idle clock lines at a later
date by using dynamic reconfiguration or a new device programming file. Clock lines
affected are unused idle receiver (RX) serial clock lines. Active RX serial clock lines
and non-transceiver circuits are not impacted by this issue.
Send Feedback
Parallel Clock
rx_clkout
(Recovered)
tx_clkout
Parallel Clock
PRBS
(From Clock
Verifier
Divider)
Parallel Clock
Serial Clock
Parallel and Serial Clock
Receiver Enhanced PCS
PRBS
Verifier
— for each receiver channel when the rate matcher is not used.
Serial Clock
— for each receiver channel when the rate matcher is used.
Receiver Standard PCS
/2, /4
rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clock
rx_pma_div_clkout
PRP
Verifier
10GBASE-R
BER Checker
on page 221
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
FPGA
Fabric
rx_coreclkin
rx_clkout or
tx_clkout
ATX PLL
CMU PLL
fPLL
Serial Clock
FPGA
Fabric
rx_clkout
221