Intel Cyclone 10 GX User Manual page 323

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
Table 176. Control and Status Register Memory Map for Embedded Reconfiguration
Streamer in ATX PLL IP
Reconfigura Reconfigura
tion tion Bit
Address
(hex)
340 7
[2:0]
341 0
Note: The soft control and status registers at x340 and x341 are enabled when you enable
the embedded reconfiguration streamer in the ATX PLL IP core.
Refer to Steps to Perform Dynamic Reconfiguration for a complete list of steps to
perform dynamic reconfiguration using the IP guided reconfiguration flow with
embedded streamer enabled. To perform a reference clock switching, use the
reconfiguration flow for special cases described in Steps to Perform Dynamic
Reconfiguration.
For the Native PHY IP, you can control the embedded streamer block through the
reconfiguration interface. Control and status signals of the streamer block are memory
mapped in the PHY's soft control and status registers. These embedded
reconfiguration control and status registers are replicated for each channel. You
cannot merge reconfiguration interfaces across multiple IP cores when the embedded
reconfiguration streamer is enabled because the embedded reconfiguration streamer
makes use of soft logic for control and status registers.
You can optionally allow the Native PHY IP core to include PMA Analog settings in the
configuration files by enabling the feature Include PMA Analog settings in
configuration files in the Dynamic Reconfirmation tab of the Transceiver Native
PHY IP Parameter Editor. This feature is disabled by default. Enabling this feature adds
the PMA analog settings specified in the Analog PMA settings (Optional) tab of the
Native PHY IP Parameter Editor to the configuration files. Even with this option
enabled in the Native PHY IP Parameter Editor, you must still specify QSF assignments
for your analog settings when compiling your static design. The analog settings
selected in the Native PHY IP Parameter Editor are used only to include these settings
and their dependent settings in the selected configuration files. For details about QSF
assignments for the analog settings, refer to the Analog Parameter Settings chapter.
For example, if the Native PHY IP core has four channels—logical channel 0 to logical
channel 3—and you want to reconfigure logical channel 3 using the embedded
reconfiguration streamer, you must write to the control register of logical channel 3
using the reconfiguration interface with the appropriate bit settings.
Note: The soft control and status registers at x340 and x341 are enabled when you enable
the embedded reconfiguration streamer in the Native PHY IP core.
Send Feedback
Attribute Attribute
Name Description
cfg_load Start
streaming
cfg_sel Configuration
profile select
rcfg_busy Busy Status
bit
Bit Transceiver Block
Encoding
1'b1 Embedded
Reconfiguration
Streamer
Direct Embedded
mapped Reconfiguration
Streamer
1'b1 Embedded
Reconfiguration
Streamer
® ®
Intel Cyclone
Description
Set to 1'b1 to initiate
streaming, self-clearing
bit
Binary encoding of the
configuration Profile to
stream
Bit is set to:
• 1'b1—streaming is in
progress
• 1'b0—streaming is
complete
10 GX Transceiver PHY User Guide
323