Intel Cyclone 10 GX User Manual page 57

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Name
rx_enh_fifo_empty[<n>
-1:0]
rx_enh_fifo_pempty[<n
>-1:0]
rx_enh_fifo_del[<n>-1
:0]
rx_enh_fifo_insert[<n
>-1:0]
rx_enh_fifo_rd_en[<n>
-1:0]
rx_enh_fifo_align_va
l[<n>-1:0]
rx_enh_fifo_align_cl
r[<n>-1:0]
Table 47. Interlaken Frame Generator, Synchronizer, and CRC32
Name
tx_enh_frame[<n>-1:0]
tx_enh_frame_diag_stat
us[<n> 2-1:0]
Send Feedback
Direction Clock Domain
the FIFO
rx_coreclkin
or
rx_clkout
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or
rx_clkout
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or
rx_clkout
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or
rx_clkout
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or
rx_clkout
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or
rx_clkout
Input Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or
rx_clkout
Input Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or
rx_clkout
Direction Clock Domain
Output
tx_clkout
Input
tx_clkout
Description
Refer to Enhanced PCS FIFO Operation
for more details.
When asserted, indicates that the RX FIFO is empty.
Because the depth is always constant, you can ignore
this signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation
for more details.
When asserted, indicates that the RX FIFO has
reached its specified partially empty threshold.
Because the depth is always constant, you can ignore
this signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation
for more details.
When asserted, indicates that a word has been deleted
from the RX FIFO. This signal gets asserted for 2 to 3
clock cycles. This signal is used for the 10GBASE-R
protocol.
When asserted, indicates that a word has been
inserted into the RX FIFO. This signal is used for the
10GBASE-R protocol.
For Interlaken only, when this signal is asserted, a
word is read form the RX FIFO. You need to control
this signal based on RX FIFO flags so that the FIFO
does not underflow or overflow.
When asserted, indicates that the word alignment
pattern has been found. This signal is only valid for
the Interlaken protocol.
When asserted, the FIFO resets and begins searching
for a new alignment pattern. This signal is only valid
for the Interlaken protocol. Assert this signal for at
least 4 cycles.
Description
Asserted for 2 or 3 parallel clock cycles to indicate the
beginning of a new metaframe.
Drives the lane status message contained in the framing
layer diagnostic word (bits[33:32]). This message is
inserted into the next diagnostic word generated by the
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
on page 164
on page 164
on page 164
continued...
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