Intel Cyclone 10 GX User Manual page 93

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 39. Rate Match FIFO Full Condition
tx_parallel_data 2D
rx_parallel_data 03
rx_std_rmfifo_full
The rate match FIFO does not insert code groups to overcome the FIFO empty
condition. It asserts the
cycles to indicate that the rate match FIFO is empty. The following figure shows the
rate match FIFO empty condition when the read pointer is faster than the write
pointer.
Figure 40. Rate Match FIFO Empty Condition
tx_parallel_data 1E 1F
rx_parallel_data 44 45
rx_std_rmfifo_empty
In the case of rate match FIFO full and empty conditions, you must assert the
rx_digitalreset
Related Information
Rate Match FIFO
2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Intel Cyclone 10 GX
Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture,
and the reset controller before implementing the GbE protocol.
1. Instantiate the Intel Cyclone 10 GX Transceiver Native PHY IP from the IP
Catalog.
Send Feedback
2E 2F 30 31
04 05 06 07
The rx_std_rmfifo_full status flag indicates
that the FIFO is full at this time
rx_std_rmfifo_empty
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signal to reset the receiver PCS blocks.
on page 310
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08 09 0A
flag for at least two recovered clock
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4A 4B 4C 4D 4E
The rx_std_rmfifo_empty status flag indicates
that the FIFO is empty at this time
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Intel Cyclone 10 GX Transceiver PHY User Guide
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