Intel Cyclone 10 GX User Manual page 114

Table 107. Types of Register Access
Access
RO Read only.
RW Read and write.
RWC Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined
instruction. The IP core clears the bit(s) upon executing the instruction.
Table 108. PHY Register Definitions
Addr
0x400
usxgmii_control
0x401
usxgmii_status
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
114
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Name
Control Register
Bit [0]:
USXGMII_ENA
• 0: 10GBASE-R mode
• 1: USXGMII mode
Bit [1]:
USXGMII_AN_ENA
is set to 1:
• 0: Disables USXGMII Auto-Negotiation and manually
configures the operating speed with the
USXGMII_SPEED
• 1: Enables USXGMII Auto-Negotiation, and
automatically configures operating speed with link
partner ability advertised during USXGMII Auto-
Negotiation.
Bit [4:2]:
USXGMII_SPEED
the PHY in USXGMII mode and
to 0.
• 3'b000: 10M
• 3'b001: 100M
• 3'b010: 1G
• 3'b011: 10G
• 3'b100: 2.5G
• 3'b101: 5G
• 3'b110: Reserved
• 3'b111: Reserved
Bit [8:5]: Reserved
Bit [9]: RESTART_AUTO_NEGOTIATION
Write 1 to restart Auto-Negotiation sequence The bit is
cleared by hardware when Auto-Negotiation is
restarted.
Bit [15:10]: Reserved
Bit [30:16]: Reserved
Status Register
Bit [1:0]: Reserved
Bit [2]:
LINK_STATUS
all speeds
• 1: Link is established
• 0: Link synchronization is lost, a 0 is latched
Bit [3]: Reserved
Definition
Description
:
is used when
USXGMII_ENA
register.
is the operating speed of
is set
USE_USXGMII_AN
indicates link status for USXGMII
UG-20070 | 2018.09.24
Access HW Reset
Value
— —
RW 0x0
RW 0x1
RW 0x0
— —
RWC 0x0
(hardw
are
self-
clear)
— —
— —
— —
— —
RO 0x0
— —
continued...
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