Intel Cyclone 10 GX User Manual page 107

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2
Transceiver Configurations
Figure 49. High BER
This figure shows the
rx_parallel_data
rx_parallel_data
rx_control
tx_parallel_data
tx_control
rx_enh_highber
Figure 50. Block Lock Assertion
This figure shows the assertion on
rx_parallel_data
rx_control
tx_parallel_data
tx_control
rx_enh_highber
rx_ready
rx_enh_block_lock
The following figures show Idle insertion and deletion.
Figure 51. IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Figure 52. IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Figure 53. OS Word Deletion
This figure shows the deletion of Ordered set word in the receiver data stream.
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Send Feedback
status signal going high when there are errors on the
rx_enh_highber
output.
1122334455667788h
0h
rx_enh_blk_lock
0100009C0100009Ch
11h
0h
0h
Before Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch
After Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch
Before Deletion
00000000000004ADh 00000000000004AEh
After Deletion
00000000000004ADh 00000000000004AEh
Before Deletion
FD000000000004AEh DDDDDD9CDDDDDD9Ch
After Deletion
FD000000000004AEh 000000FBDDDDDD9Ch
1122324455667788h 112233405566F788h
00h
1122334455667788h
00h
signal when the Receiver detects the block delineation.
0707070707070707h
FFh
00000000000000FBh
0707070707070707h
0707070707FD0000h
0707070707FD0000h
Idle Deleted
00000000000000FBh
AAAAAAAA00000000h
OS Deleted
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
1122334455667788h
1h
0707070707070707h
FFh
1h
1h
AAAAAAAAAAAAAAAAh
00000000000000FBh
Idle Inserted
000000FB07070707h
AAAAAAAA000000FBh
AAAAAAAAAAAAAAAAh
00000000AAAAAAAAh
107