Interlaken Configuration Clocking And Bonding - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
The
tx_enh_frame_diag_status[1:0]
the Status field each time a DIAG word is created by the framing generator.
Figure 20. Interlaken Diagnostic Word
bx10 b011001
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2.5.2. Interlaken Configuration Clocking and Bonding

The Cyclone 10 GX Interlaken PHY layer solution is scalable and has flexible data
rates. You can implement a single lane link or bond up to 48 lanes together. You can
choose a lane data rate up to 12.5 Gbps. You can also choose between different
reference clock frequencies, depending on the PLL used to clock the transceiver.
You can use an ATX PLL or fPLL to provide the clock for the transmit channel. An ATX
PLL has better jitter performance compared to an fPLL. You can use the CMU PLL to
clock only the non-bonded Interlaken transmit channels. However, if you use the CMU
PLL, you lose one RX transceiver channel.
For the multi-lane Interlaken interface, TX channels are usually bonded together to
minimize the transmit skew between all bonded channels. Currently, xN bonding and
PLL feedback compensation bonding schemes are available to support a multi-lane
Interlaken implementation. If the system tolerates higher channel-to-channel skew,
you can choose to not bond the TX channels.
To implement bonded multi-channel Interlaken, all channels must be placed
contiguously. The channels may all be placed in one bank (if not greater than six
lanes) or they may span several banks.
Related Information
Using PLLs and Clock Networks
For more information about implementing PLLs and clocks
2.5.2.1. xN Clock Bonding Scenario
The following figure shows a xN bonding example supporting 10 lanes. Each lane is
running at 12.5 Gbps. The first six TX channels reside in one transceiver bank and the
other four TX channels reside in the adjacent transceiver bank. The ATX PLL provides
the serial clock to the master CGB. The CGB then provides parallel and serial clocks to
all of the TX channels inside the same bank and other banks through the xN clock
network.
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h000000
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input from the FPGA fabric is inserted into
Status CRC32
34 33 32 31
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Intel Cyclone 10 GX Transceiver PHY User Guide
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