Intel Cyclone 10 GX User Manual page 249

4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Clock Data Recovery in Auto Lock Mode
The step numbers correspond to the numbers in the following figure:
1. Assert
low. You must reset the PCS by asserting
assert
2. Deassert
3. Ensure
deasserting
Figure 150. Resetting the Receiver During Device Operation (Auto Mode)
Note:
rx_is_lockedtodata
rx_is_lockedtoref
Clock Data Recovery in Manual Lock Mode
Use the clock data recovery (CDR) manual lock mode to override the default CDR
automatic lock mode depending on your design requirements.
Related Information
"Transceiver PHY Reset Controller IP Core" chapter of the Altera Transceiver PHY IP
Core User Guide.
Refer to the description of the
table for information about using the manual lock mode.
Control Settings for CDR Manual Lock Mode
Use the following control settings to set the CDR lock mode:
Table 157. Control Settings for the CDR in Manual Lock Mode
rx_set_locktoref
0
1
X
Send Feedback
and
rx_analogreset
.
rx_analogreset
after a minimum duration of 70 μs.
rx_analogreset
rx_is_lockedtodata
rx_digitalreset
Device Power Up
rx_cal_busy
rx_analogreset
rx_is_lockedtodata
rx_digitalreset
t = 70 μs
req
1
will toggle when there is no data at the receiver input.
is a "do not care" when
rx_set_locktodata
0
0
1
. Ensure that
rx_digitalreset
rx_digitalreset
is asserted for t (minimum of 4 μs) before
LTD
.
t
req
2
rx_is_lockedtodata
signal in the "Top-Level Signals"
rx_digitalreset
Automatic
Manual-RX CDR LTR
Manual-RX CDR LTD
®
Intel Cyclone
rx_cal_busy
every time you
t min 4 μs
LTD
3
is asserted.
CDR Lock Mode
®
10 GX Transceiver PHY User Guide
is
249