Direct Reconfiguration Flow - Intel Cyclone 10 GX User Manual

If you reconfigured:
• PLLs—Release the reset (analog) of the channel transmitters associated with
the PLL reconfigured.
• TX simplex channels—Release the reset (analog) of the TX channels
reconfigured.
• RX simplex channels—Release the reset (analog) of the RX channels
reconfigured.
• Duplex channels—Release the reset (analog) of the TX and RX channels
reconfigured.
12. Release the channel digital resets either simultaneously or one after another. For
details about releasing the channel resets, refer to "Model 1: Default Model" and
"Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter.
(The figures in these sections are for analog resets, but they also contain timing
information about digital resets.)
If you reconfigured:
• PLLs—Release the reset (digital) of the channel transmitters associated with
the PLL reconfigured.
• TX simplex channels—Release the reset (digital) of the TX channels
reconfigured.
• RX simplex channels—Release the reset (digital) of the RX channels
reconfigured.
• Duplex channels—Release the reset (digital) of the TX and RX channels
reconfigured.
Note: You cannot merge multiple reconfiguration interfaces across multiple IP blocks
(merging independent instances of simplex TX/RX into the same physical location or
merging separate CMU PLL and TX channel into the same physical location) when you
use the optional reconfiguration logic soft control registers.
Related Information
• Resetting Transceiver Channels
• Model 1: Default Model
• Model 2: Acknowledgment Model
•

Direct Reconfiguration Flow

• Native PHY IP or PLL IP Core Guided Reconfiguration Flow
• Reconfiguration Flow for Special Cases
• Changing PMA Analog Parameters
• Calibration
• Arbitration
6.9. Direct Reconfiguration Flow
Use this flow to perform dynamic reconfiguration when you know exactly which
parameter and value to change for the transceiver channel or PLL. You can use this
flow to change the PMA analog settings, enable/disable PRBS generator, and checker
hard blocks of the transceiver channel.
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Intel Cyclone 10 GX Transceiver PHY User Guide
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6. Reconfiguration Interface and Dynamic Reconfiguration
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