Intel Cyclone 10 GX User Manual page 162

Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_serialpbken port
Enable PRBS verifier control and status ports
Table 144. Enhanced PCS Parameters
Enhanced PCS/PMA interface width
FPGA fabric/Enhanced PCS interface width
Enable Enhanced PCS low latency mode
Enable RX/TX FIFO double width mode
TX FIFO mode
TX FIFO partially full threshold
TX FIFO partially empty threshold
Enable tx_enh_fifo_full port
Enable tx_enh_fifo_pfull port
Enable tx_enh_fifo_empty port
Enable tx_enh_fifo_pempty port
RX FIFO mode
RX FIFO partially full threshold
RX FIFO partially empty threshold
Enable RX FIFO alignment word deletion (Interlaken)
Enable RX FIFO control word deletion (Interlaken)
Enable rx_enh_data_valid port
Enable rx_enh_fifo_full port
Enable rx_enh_fifo_pfull port
Enable rx_enh_fifo_empty port
Enable rx_enh_fifo_pempty port
Enable rx_enh_fifo_del port (10GBASE-R)
Enable rx_enh_fifo_insert port (10GBASE-R)
Enable rx_enh_fifo_rd_en port
Enable rx_enh_fifo_align_val port (Interlaken)
Enable rx_enh_fifo_align_cir port (Interlaken)
Enable TX 64b/66b encoder
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Intel Cyclone 10 GX Transceiver PHY User Guide
162
Parameter
Parameter
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
On / Off
On / Off
On / Off
On / Off
On / Off
32, 40, 64
32, 40, 50, 64, 66, 67
On / Off
On / Off
Phase compensation, Register, Interlaken, Basic, Fast
register
Note: Only Basic Enhanced is valid.
10, 11, 12, 13, 14, 15
1, 2, 3, 4, 5
On / Off
On / Off
On / Off
On / Off
Phase Compensation, Register, Basic
0 to 31
0 to 31
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
UG-20070 | 2018.09.24
Range
Range
continued...
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