Intel Cyclone 10 GX User Manual page 374

There are two ways to check who has the access to the internal configuration bus:
•
Use
reconfig_waitrequest
• Use capability registers
The Native PHY IP core and PLL default setting is to use
When PreSICE controls the internal configuration bus, the
from the internal configuration bus is high. When user access is granted, the
reconfig_waitrequest
MM reconfiguration interface, the
places inside Native PHY IP core. For example, it can come from the internal
configuration bus, streamer, and so on. They are bundled together and become single
reconfig_waitrequest
reconfig_address
Avalon-MM reconfiguration interface. After you return the internal configuration bus to
PreSICE, the
you set the
reconfiguration interface during calibration, the
before calibration is finished. If you keep the
internal configuration bus offset address during calibration, the
reconfig_waitrequest
PreSICE returns the internal configuration bus to you. It is important to keep
reconfig_address static during calibration.
To use capability registers to check bus arbitration, you can do the following when
generating the IP:
1. Select Enable dynamic reconfiguration from the Dynamic Reconfiguration
tab.
2. Select both the Separate reconfig_waitrequest from the status of AVMM
arbitration with PreSICE and Enable control and status registers options.
You can read the capability register 0x281[2] to check who is controlling the channel
access, and read the capability register 0x280[2] to check who is controlling the PLL
access. When Separate reconfig_waitrequest from the status of AVMM
arbitration with PreSICE and Enable control and status registers are enabled,
the
reconfig_waitrequest
internal configuration bus.
To return the internal configuration bus to PreSICE:
• Write 0x1 to offset address 0x0[7:0] if any calibration bit is enabled from
offset address 0x100.
• Write 0x3 to offset address 0x0[7:0] if no calibration bit has been
enabled from offset address 0x100.
To check if the calibration process is running, do one of the following:
•
Monitor the
•
Read the
The
*_cal_busy
running. To check whether or not calibration is done, you can read the capability
registers or check the
Avalon-MM reconfiguration interface is not a reliable indicator to check whether or not
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
374
from the internal configuration bus goes low. At the Avalon-
reconfig_waitrequest
at the Avalon-MM reconfiguration interface. The
determines which
reconfig_waitrequest
to the streamer offset address at the Avalon-MM
reconfig_address
at the Avalon-MM reconfiguration interface will be high until
will not be asserted high when PreSICE controls the
,
pll_cal_busy tx_cal_busy
signal status from the capability registers.
*_cal_busy
signals remain asserted as long as the calibration process is
*_cal_busy
reconfig_waitrequest
reconfig_waitrequest
reconfig_waitrequest
from the internal configuration bus is high. If
reconfig_waitrequest
reconfig_address
, and
rx_cal_busy
signals. The
reconfig_waitrequest
7. Calibration
UG-20070 | 2018.09.24
.
can come from a few
to show at the
can be low
the same as the
signals.
from the
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