Intel Cyclone 10 GX User Manual page 134

Parameter
RX FIFO mode
Enable
tx_std_pcfifo_full
Enable
tx_std_pcfifo_empty
Enable
rx_std_pcfifo_full
Enable
rx_std_pcfifo_empty
Byte Serializer and Deserializer
TX byte serializer mode
RX byte deserializer mode
8B/10B Encoder and Decoder
Enable TX 8B/10B encoder
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
Rate Match FIFO
Rate Match FIFO mode
RX rate match insert / delete -ve pattern (hex)
RX rate match insert / delete +ve pattern (hex)
Enable
rx_std_rmfifo_full
Enable
rx_std_rmfifo_empty
Word Aligner and Bit Slip
Enable TX bit slip
Enable
tx_std_bitslipboundarysel
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Number of word alignment patterns to achieve
sync
Number of invalid data words to lose sync
Number of valid data words to decrement error
count
Enable
rx_std_wa_patternalign
Enable
rx_std_wa_a1a2size
Enable
rx_std_bitslipboundarysel
Enable port
rx_bitslip
Bit Reversal and Polarity Inversion
Enable TX bit reversal
Enable TX byte reversal
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
134
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
port
port
port
port
Disabled, Serialize x2
Disabled, Serialize x2
0x0002f17c (K28.5/K28.0/)
0x000d0e83 (K28.5/K28.0/)
port
port
port
Synchronous State Machine
0x0000 00000000017c (/K28.5/)
port
port
port
Gen1 PIPE
low_latency
Optional
Optional
Optional
Optional
Enabled
Enabled
Enabled
PIPE, PIPE 0ppm
Optional
Optional
Off
Optional
10
0x0000 00000000017c (/K28.5/)
3
16
15
Optional
Off
Optional
Off
Off
Off
UG-20070 | 2018.09.24
Gen2 PIPE
low_latency
Optional
Optional
Optional
Optional
Serialize x2
Serialize x2
Enabled
Enabled
Enabled
PIPE, PIPE 0ppm
0x0002f17c (K28.5/K28.0/)
0x000d0e83 (K28.5/K28.0/)
Optional
Optional
Off
Optional
Synchronous State Machine
10
3
16
15
Optional
Off
Optional
Off
Off
Off
continued...
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