How To Implement Pcs Direct Transceiver Configuration Rule - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Enable PCIe pipe_hclk_in and pipe_hclk_out ports
Enable PCIe electrical idle control and status ports
Enable PCIe pipe_rx_polarity port
Table 151. Dynamic Reconfiguration Parameters
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master Endpoint
Table 152. Generation Options Parameters
Generate parameter documentation file
Related Information
Using the Cyclone 10 GX Transceiver Native PHY IP Core

2.9.3. How to Implement PCS Direct Transceiver Configuration Rule

You should be familiar with PCS Direct architecture, PMA architecture, PLL
architecture, and the reset controller before implementing PCS Direct Transceiver
Configuration Rule.
1. Open the IP Catalog and select Cyclone 10 GX Transceiver Native PHY IP.
2. Select PCS Direct from the Transceiver configuration rules list located under
Datapath Options.
3. Configure your Native PHY IP.
4. Click Generate to generate the Native PHY IP (this is your RTL file).
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller. You can use your own controller or use the
Transceiver PHY Reset Controller.
7. Connect the Native PHY IP to the PLL IP and the reset controller.
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Parameter
Parameter
Parameter
Range
Off
Off
Off
Range
On/Off
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