Implementing Protocols In Intel Cyclone 10 Gx Transceivers Revision History - Intel Cyclone 10 GX User Manual

Simulator
Synopsys VCS /simulation/synopsys/vcs/
vcs_setup.sh
Synopsys VCS MX /simulation/synopsys/
vcsmx/vcsmx_setup.sh
Cadence Incisive /simulation/cadence/
(NCSim) ncsim_setup.sh
2.11. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Revision History
Document
Version
2018.09.24 Made the following changes to the "Using the Cyclone 10 GX Transceiver Native PHY IP Core" section:
• Added details about how to enable the transceiver toolkit capability in the "Dynamic Reconfiguration
Parameters" section.
Made the following changes to the "1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core"
section"
• Added this section.
2017.12.04 Made the following changes:
•
Removed the
2017.11.30 Made the following changes in the "PCI Express" section:
• Removed the following parameters from the "Parameters for Intel Cyclone 10 GX Native PHY IP in
PIPE Gen1, Gen2 Modes - TX PMA" table:
— Enable tx_pma_qpipullup port (QPI)
— Enable tx_pma_qpipulldn port (QPI)
— Enable tx_pma_txdetectrx port (QPI)
— Enable tx_pma_rxfound port (QPI)
• Removed the Enable rx_pma_qpipulldn port (QPI) parameter from the "Parameters for Intel
Cyclone 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes - RX PMA" table.
Made the following changes to the "Using the Transceiver Native PHY IP Core" section:
• Removed the QPI protocol mode from the PMA configuration rules parameter in the "General,
Common PMA Options, and Datapath Options" table.
• Removed the following parameters from the "TX PMA Parameters" table:
— Enable tx_pma_qpipullup port (QPI)
— Enable tx_pma_qpipulldn port (QPI)
— Enable tx_pma_txdetectrx port (QPI)
— Enable tx_pma_rxfound port (QPI)
2017.11.06 Made the following changes to the "Other Protocols" section:
• Changed Native PHY IP data rate to 12.5 from 10.3125
Made the following changes to the "PCI Express" section:
•
Added note "Connect
Native PHY" in figure "Use fPLL for Gen1/Gen2 x1 Mode".
• Changed the clock frequency differential in the "Gen1 and Gen2 Clock Compensation" section
introduction paragraph.
Made the following changes to the "Transceiver Design Flow Overview" section:
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
196
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Simulation File
Add your testbench file name to this file to pass the testbench file
to VCS using the
NativeLink and do not choose to simulate, NativeLink generates a
script that runs VCS.
Run this script at the command line using
<script>
in this script.
Run this script at the command line using
<script>. Any testbench you specify with NativeLink is included in
this script.
tx_pma_txdetectrx[<n>-1:0]
pll_pcie_clk
Use
option. If you specify a testbench file for
–file
. Any testbench you specify with NativeLink is included
Changes
port from the "TX PMA Ports" table.
from either ATX PLL or fPLL to the
UG-20070 | 2018.09.24
quartus_sh–t
quartus_sh –t
port on
pipe_hclk_in
continued...
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