Intel Cyclone 10 GX User Manual page 270

Figure 166. Physical Routing Delay Skew in Bonded Channels
You must provide a Synopsys Design Constraint (SDC) for the reset signals to
guarantee that your design meets timing requirements. The Quartus Prime software
generates an
This
.sdc
In the case of bonded designs, this file contains examples for maximum skew on
bonded designs. This
max_skew
All modified IP constraints from a generated
main
.sdc
This skew is present whether you tie all
them separately. If your design includes the Transceiver PHY Reset Controller IP core,
you can substitute your instance and interface names for the generic names shown in
the example.
Example 1. SDC Constraint for TX Digital Reset When Bonded Clocks Are Used
set_max_skew -from *<IP_INSTANCE_NAME> *tx_digitalreset*r_reset
-to *pld_pcs_interface* <1/2 coreclk period in ps>
In the above example, you must make the following substitutions:
• <IP_INSTANCE_NAME>—substitute the name of your reset controller IP instance
or PHY IP instance
• <½ coreclk period in ps>—substitute half of the clock period of your design in
picoseconds
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
270
FPGA Fabric
PHY Reset
Controller
tx_digitalreset
file when you generate the Transceiver Native PHY IP core.
.sdc
contains basic false paths for most asynchronous signals, including resets.
file contains an example
.sdc
constraint for the
tx_digitalreset
file, because changes will be lost if the IP is regenerated.
4. Resetting Transceiver Channels
TX
Channel[ n - 1]
TX
Channel[1]
TX
Channel[0]
false_path
signals.
file must be moved to the project's
.sdc
together, or you control
tx_digitalresets
UG-20070 | 2018.09.24
Bonded TX
Channels
and an example
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