Other Protocols; Using The "Basic (Enhanced Pcs)" Configuration - Intel Cyclone 10 GX User Manual

Table 139. Dynamic Reconfiguration
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master Endpoint
Enable embedded debug
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Enable prbs soft accumulators
Configuration file prefix
Generate SystemVerilog package file
Generate C header file
Generate MIF (Memory Initialization File)
Table 140. Generation Options
Generate parameter documentation file

2.9. Other Protocols

2.9.1. Using the "Basic (Enhanced PCS)" Configuration

You can use Cyclone 10 GX transceivers to configure the Enhanced PCS to support
other 10G or 10G-like protocols. The Basic (Enhanced PCS) transceiver configuration
rule allows access to the Enhanced PCS with full user control over the transceiver
interfaces, parameters, and ports.
You can configure the transceivers for Basic functionality using the Native PHY IP
Basic (Enhanced PCS) transceiver configuration rule.
Note: This configuration supports the FIFO in phase compensation and register modes. You
can implement all other required logic for your specific application, such as standard
or proprietary protocol multi-channel alignment in the FPGA fabric in soft IP.
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Intel Cyclone 10 GX Transceiver PHY User Guide
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2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Parameter
Parameter
UG-20070 | 2018.09.24
Value
Off
Off
Off
Off
Off
0
Off
Off
altera_xcvr_native_c10
Off
Off
Off
Value
On
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