Intel Cyclone 10 GX User Manual page 361

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
The PRBS checker has the following control and status signals available to the FPGA
fabric:
•
rx_prbs_done
stays high until you reset it with
•
rx_prbs_err
allow you to capture it in the RX FPGA CLK domain.
•
rx_prbs_err_clr
Enable the PRBS checker control and status ports through the Native PHY IP
Parameter Editor in the Quartus Prime software.
Use the PRBS soft accumulators to count the number of accumulated bits and errors
when the hard PRBS blocks are used. For more information about using the
accumulators and reading the error values, refer to the PRBS Soft Accumulators
section.
Table 203. Register Map for PRBS Generators for bonded and non bonded designs
Description
Select PRBS 0x006
generator block
0x008
Enable PRBS 9 in 0x006
10-bit mode
Enable PRBS 9 in
64-bit mode
Enable PRBS 0x006
generator clock
Disable PRBS
generator clock
Enable PRBS 7 0x007
pattern
0x008
Enable PRBS 9 0x007
pattern
0x008
Enable PRBS 15 0x007
pattern
0x008
Enable PRBS 23 0x007
pattern
0x008
enable PRBS 31 0x007
pattern
0x008
Serializer 64-bit 0x110
width mode
Serializer 10-bit
width mode
Enable xN non 0x111
bonding
0x119
Send Feedback
—Indicates the PRBS sequence has completed one full cycle. It
—Goes high if an error occurs. This signal is pulse-extended to
—Used to reset the
Reconfiguration Reconfiguration
Address Bits
[2:0]
[6:5]
[3]
[6]
[7:4]
[4]
[7:4]
[4]
[7:4]
[4]
[7:4]
[4]
[7:4]
[4]
[2:0]
[4:0]
[0]
.
rx_prbs_err_clr
rx_prbs_err signal
Value Attribute Encoding
3'b100 prbs_pat
2'b00
1'b1 prbs9_10b
1'b0 prbs9_64b
1'b1 prbs_clk_en
1'b0 prbs_clk_dis
4'b0001 prbs_7
1'b0
4'b0010 prbs_9
1'b0
4'b0100 prbs_15
1'b0
4'b1000 prbs_23
1'b0
4'b0000 prbs_31
1'b1
3'b011 sixty_four_bit
3'b100 ten_bit
5'b11000 xN_non_bonding
1'b0
® ®
Intel Cyclone
.
Attribute Name
tx_pma_data_sel
prbs9_dwidth
prbs_clken
prbs_gen_pat
ser_mode
(31)
x1_clock_source_sel
10 GX Transceiver PHY User Guide
361