Intel Cyclone 10 GX User Manual page 112

Figure 55. Architecture of 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration
Intel Stratix 10 FPGA Device
LL Ethernet
10G MAC
Avalon-ST
Interface
User
Application
Legend
In the transmit direction, the PHY encodes the Ethernet frame as required for reliable
transmission over the media to the remote end. In the receive direction, the PHY
passes frames to the MAC.
Note: You can generate the MAC and PHY design example using the Low Latency Ethernet
10G MAC Intel FPGA IP Parameter Editor.
The IP core includes the following interfaces:
• Datapath client-interface:
— 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
• Management interface—Avalon-MM host slave interface for PHY management.
• Datapath Ethernet interface with the following available options:
— 10M/100M/1G/2.5G/5G/10G (USXGMII) —Single 10.3125 Gbps serial link
• Transceiver PHY dynamic reconfiguration interface—an Avalon-MM interface to
read and write the Intel Cyclone 10 GX Native PHY IP core registers. This interface
supports dynamic reconfiguration of the transceiver. It is used to configure the
transceiver operating modes to switch to desired Ethernet operating speeds.
The 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration supports the following
features:
• USXGMII—10M/100M/1G/2.5G/5G/10G speeds
• Full duplex data transmission
• USXGMII Auto-Negotiation
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Intel Cyclone 10 GX Transceiver PHY User Guide
112
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
10M/100M/1G/2.5G/5G/10G Multi-rate Ethernet PHY
TX
32-bit XGMII
Soft PCS
RX
32-bit XGMII
Configuration
registers
Avalon-MM
Interface
Transceiver
Reconfiguration Block
Reset
Controller
Hard IP
Soft Logic
Native PHY Hard IP
Hard PCS PMA
PLL
for 10 GbE
322-MHz or 644-MHz
Reference Clock
UG-20070 | 2018.09.24
TX Serial
External
PHY
RX Serial
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