Combining Status Or Pll Lock Signals; Timing Constraints For Bonded Pcs And Pma Channels - Intel Cyclone 10 GX User Manual

4. Resetting Transceiver Channels
UG-20070 | 2018.09.24

4.6. Combining Status or PLL Lock Signals

You can combine multiple PHY status signals before feeding into the reset controller as
shown below.
Figure 164. Combining Multiple PHY Status Signals
tx_cal_busy signals
from channels
Note:
This configuration also applies to the
When using multiple PLLs, you can logical AND the
reset controller. Similarly, you can logical OR the
controller
Figure 165. Multiple PLL Configuration
pll_lock signals
from PLLs
pll_cal_busy and
tx_cal_busy
signals
Resetting different channels separately requires multiple reset controllers. For
example, a group of channels configured for Interlaken requires a separate reset
controller from another group of channels that are configured for optical
communication.

4.7. Timing Constraints for Bonded PCS and PMA Channels

For designs that use TX PMA and PCS Bonding, the digital reset signal
(
tx_digitalreset
maximum skew tolerance imposed by physical routing. This skew tolerance is one-half
the TX parallel clock cycle (
PMA Bonding or for RX PCS channels.
Note: If the design is not able to meet the maximum skew tolerance requirement with a
positive margin, Intel recommends reassigning the channels' locations that are not
adjacent to the PCIe Hard IP block.
Send Feedback
AND
port as shown below.
tx_cal_busy
AND
AND
) to all TX channels within a bonded group must meet a
tx_clkout
OR
signals.
rx_cal_busy
pll_locked
pll_cal_busy
OR
). This requirement is not necessary for TX
®
Intel Cyclone
To reset controller
tx_cal_busy input port
signals feeding the
signals to the reset
To reset controller
pll_locked input port
To reset controller
tx_cal_busy input port
®
10 GX Transceiver PHY User Guide
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