Configure The Phy Ip Core; Generate The Phy Ip Core; Select The Pll Ip Core - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24

2.2.2. Configure the PHY IP Core

Configure the PHY IP core by selecting the valid parameters for your design. The valid
parameter settings are different for each protocol. Refer to the appropriate protocol's
section for selecting valid parameters for each protocol.

2.2.3. Generate the PHY IP Core

After configuring the PHY IP, complete the following steps to generate the PHY IP.
1. Click the Generate HDL button in the Parameter Editor window. The
Generation dialog box opens.
2. In Synthesis options, under Create HDL design for synthesis select
or
VHDL
3. Select appropriate Simulation options depending on the choice of the hardware
description language you selected under Synthesis options.
4. In Output Directory, select Clear output directories for selected generation
targets if you want to clear any previous IP generation files from the selected
output directory.
5. Click Generate.
The Quartus Prime software generates a <phy ip instance name> folder, <phy ip
instance name>_sim folder, <phy ip instance name>.qip file, <phy ip instance
name>.qsys file, and <phy ip instance name>.v file or <phy ip instance name>.vhd
file. This <phy ip instance name>.v file is the top level design file for the PHY IP and is
placed in the <phy ip instance name>/synth folder. The other folders contain lower
level design files used for simulation and compilation.
Related Information
IP Core File Locations
For more information about IP core file structure

2.2.4. Select the PLL IP Core

Cyclone 10 GX devices have three types of PLL IP cores:
• Advanced Transmit (ATX) PLL IP core.
• Fractional PLL (fPLL) IP core.
• Channel PLL / Clock Multiplier Unit (CMU) PLL IP core.
Select the appropriate PLL IP for your design. For additional details, refer to the PLLs
and Clock Networks chapter.
To instantiate a PLL IP:
1. Open the Quartus Prime software.
2. Click Tools
3. At the top of the IP Catalog window, select Cyclone 10 GX device family
4. In IP Catalog, under Library
PLL choose the PLL IP ( Cyclone 10 GX fPLL, Cyclone 10 GX Transceiver
ATX PLL, or Cyclone 10 GX Transceiver CMU PLL) you want to include in your
design and then click Add.
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on page 67
IP Catalog.
Basic Functions Clocks, PLLs, and Resets
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Intel Cyclone
Verilog
10 GX Transceiver PHY User Guide
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