Intel Cyclone 10 GX User Manual page 144

Port
tx_serial_clk
pll_locked
pll_pcie_clk
Pll_cal_busy
Mcgb_rst
tx_bonding_clocks[5:0]
pcie_sw[1:0]
pcie_sw_done[1:0]
Related Information
Using the Cyclone 10 GX Transceiver Native PHY IP Core
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
144
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Direction Clock Domain
Output N/A
Output Asynchronous
Output N/A
Output Asynchronous
Input Asynchronous
] Output N/A
Input Asynchronous
Output Asynchronous
Description
High speed serial clock output port for GX channels.
Represents the x1 clock network.
For Gen1x1, Gen2x1, connect the output from this port to the
input of the native PHY IP.
tx_serial_clk[5:0]
For Gen1x2, x4 use the
tx_bonding_clocks[5:0]
port to connect to the Native PHY IP.
For Gen2x2, x4 use the
tx_bonding_clocks
connect to the Native PHY IP.
Active high status signal which indicates if PLL is locked.
This is the hclk required for PIPE interface.
For Gen1x1, x2, x4 use this port to drive the
for the PIPE interface.
pipe_hclk_in
For Gen2x1, x2, x4 use this port to drive the
for the PIPE interface.
Status signal which is asserted high when PLL calibration is in
progress.
If this port is not enabled in Transceiver PHY Reset Controller,
then perform logical OR with this signal and the
output signal from Native PHY to input the
the reset controller IP.
Master CGB reset control.
Optional 6-bit bus which carries the low speed parallel clock
outputs from the Master CGB. It is used for channel bonding,
and represents the x6/xN clock network.
For Gen1x1, this port is disabled.
For Gen1x2, x4 connect the output from this port to the
input on Native PHY.
tx_bonding_clocks
For Gen2x1, this port is disabled.
For Gen2x2, x4 connect the output from this port to the
input on Native PHY.
tx_bonding_clocks
2-bit rate switch control input used for PCIe protocol
implementation.
For Gen1, this port is N/A
For Gen 2x2, x4 connect the
pipe_sw
to this port.
2-bit rate switch status output used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen 2x2, x4 connect the
pcie_sw_done[1:0]
from fPLL to the
pipe_sw_done
on page 26
UG-20070 | 2018.09.24
output
output port to
pipe_hclk_in
tx_cal_busy
on
tx_cal_busy
output from Native PHY
output
input of Native PHY .
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