Intel Cyclone 10 GX User Manual page 309

5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
PCS-PMA Supported Word
Interface Aligner Modes
Width
Manual
Deterministic latency
(CPRI mode only)
Synchronous State
Machine
5.3.2.1.6. Word Aligner RX Bit Reversal Feature
The RX bit reversal feature reverses the order of the data received from the PMA. It is
performed at the output of the Word Aligner and is available even when the Word
Aligner is disabled. If the data received from the PMA is a 10-bit data width, the bit
reversal feature switches bit [0] with bit [9], bit [1] with bit [8], and so on. For
example, if the 10-bit data is 1000010011, the bit reversal feature, when enabled,
changes the data to 1100100001.
5.3.2.1.7. Word Aligner RX Byte Reversal Feature
The RX byte reversal feature is available only when the PCS-PMA interface width is 16
bits or 20 bits. This feature reverses the order of the data received from the PMA. RX
byte reversal reverses the LSByte of the received data with its MSByte and vice versa.
If the data received is 20-bits, bits[0..9] are swapped with bits[10..20] so that the
Send Feedback
Supported
rx_std_wa_patte
Word Aligner
behavior
rnalign
Pattern
Lengths
double width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
7, 10, 20, 40 Word alignment is
controlled by rising
edge of
rx_std_wa_patt
.
ernalign
10 Word alignment is
controlled by
rx_std_wa_patt
(edge-
ernalign
sensitive to this
signal) and the
deterministic
latency state
machine which
controls the PMA to
achieve
deterministic
latency on the RX
path for CPRI and
OBSAI applications.
7, 10, 20 FPGA fabric-driven
rx_std_wa_patt
signal
ernalign
has no effect on
word alignment.
rx_syncstatus rx_patterndetect
behavior
Stays high after Asserted high for
the word aligner one parallel clock
aligns to the word cycle when the word
alignment pattern. alignment pattern
Goes low on appears in the
receiving a rising current word
edge on boundary.
rx_std_wa_patt
until a
ernalign
new word
alignment pattern
is received.
— —
Stays high as long Asserted high for
as the one parallel clock
synchronization cycle when the word
conditions are alignment pattern
satisfied. appears in the
current word
boundary.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
behavior
309