Intel Cyclone 10 GX User Manual page 276

Figure 171. Receiver PMA Block Diagram
Receiver Serial
Differential Input
5.1.2.1. Receiver Buffer
The receiver input buffer receives serial data from
serial data to the clock data recovery (CDR) unit and deserializer.
Figure 172. Receiver Buffer
From Serial Data
(rx_serial_data)
R1* - Half of the actual on-chip termination selected
The receiver buffer supports the following features:
• Programmable common mode voltage (V
• Programmable differential On-Chip Termination (OCT)
• Signal Detector
• Continuous Time Linear Equalization (CTLE)
• Variable Gain Amplifiers (VGA)
5.1.2.1.1. Programmable Common Mode Voltage (V
The receiver buffer has on-chip biasing circuitry to establish the required V
receiver input.
The Quartus Prime software automatically chooses the optimal setting for RX V
Note: On-chip biasing circuitry is available only if you select OCT. If you select external
termination, you must implement off-chip biasing circuitry to establish the V
receiver input buffer.
Manual V
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
276
Receiver PMA
Serial
Data
Receiver
Buffer
Data
Input Pins
Termination
R1*
85Ω, 100Ω, OFF
adjustment is not supported and is only adjusted by calibrations.
CM
5. Cyclone 10 GX Transceiver PHY Architecture
Serial
Data
CDR Deserializer
Serial Clock
Parallel Clock
rx_serial_data
RX
R1*
RX
V
CM
)
CM
)
CM
UG-20070 | 2018.09.24
Parallel Parallel Data
Receiver
Data to FPGA Core
PCS
and feeds the
CTLE
VGA
To CDR
at the
CM
CM
at the
CM
Send Feedback
.