Resetting Transceiver Channels Revision History - Intel Cyclone 10 GX User Manual

4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
If your design has custom reset logic, replace the
*<IP_INSTANCE_NAME>*tx_digitalreset*r_reset
the TX PCS reset signal,
For more information about the
Timing Analyzer API Reference Manual.
Related Information
SDC and TimeQuest API Reference Manual

4.8. Resetting Transceiver Channels Revision History

Document
Version
2017.11.06 Made the following changes:
• Added a note "If the design is not able to meet the maximum skew tolerance requirement with a
positive margin, Intel recommends reassigning the channels locations that are not adjacent to the
PCIe Hard IP block."
2017.05.08 Initial release.
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.
tx_digitalreset
set_max_skew
Changes
Intel
with the source register for
constraint, refer to the SDC and
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Cyclone 10 GX Transceiver PHY User Guide
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